Searched hist:"1 fa3a634137c9f40b207cff1079fe0dfbd9b3378" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/board/nvidia/dalmore/ |
| H A D | pinmux-config-dalmore.h | 1fa3a634137c9f40b207cff1079fe0dfbd9b3378 Fri Mar 21 18:29:00 UTC 2014 Stephen Warren <swarren@nvidia.com> ARM: tegra: Tegra114 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra114/ |
| H A D | pinmux.h | 1fa3a634137c9f40b207cff1079fe0dfbd9b3378 Fri Mar 21 18:29:00 UTC 2014 Stephen Warren <swarren@nvidia.com> ARM: tegra: Tegra114 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|