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| /rk3399_rockchip-uboot/include/configs/ |
| H A D | omapl138_lcdk.h | 1601dd97edc643e4f033851729a9f5ba01655e2b Thu Dec 01 11:07:43 UTC 2016 Bartosz Golaszewski <bgolaszewski@baylibre.com> davinci: omapl138_lcdk: increase PLL0 frequency
The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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