Searched hist:"12 e7c4ab0bbc9d9d4e950bdbda5a86f61c13bc1a" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cpu_helpers.S | 12e7c4ab0bbc9d9d4e950bdbda5a86f61c13bc1a Thu Jan 29 18:27:38 UTC 2015 Vikram Kanigiri <vikram.kanigiri@arm.com> Initialise cpu ops after enabling data cache
The cpu-ops pointer was initialized before enabling the data cache in the cold
and warm boot paths. This required a DCIVAC cache maintenance operation to
invalidate any stale cache lines resident in other cpus.
This patch moves this initialization to the bl31_arch_setup() function
which is always called after the data cache and MMU has been enabled.
This change removes the need:
1. for the DCIVAC cache maintenance operation.
2. to initialise the CPU ops upon resumption from a PSCI CPU_SUSPEND
call since memory contents are always preserved in this case.
Change-Id: Ibb2fa2f7460d1a1f1e721242025e382734c204c6
|
| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | bl31_entrypoint.S | 12e7c4ab0bbc9d9d4e950bdbda5a86f61c13bc1a Thu Jan 29 18:27:38 UTC 2015 Vikram Kanigiri <vikram.kanigiri@arm.com> Initialise cpu ops after enabling data cache
The cpu-ops pointer was initialized before enabling the data cache in the cold
and warm boot paths. This required a DCIVAC cache maintenance operation to
invalidate any stale cache lines resident in other cpus.
This patch moves this initialization to the bl31_arch_setup() function
which is always called after the data cache and MMU has been enabled.
This change removes the need:
1. for the DCIVAC cache maintenance operation.
2. to initialise the CPU ops upon resumption from a PSCI CPU_SUSPEND
call since memory contents are always preserved in this case.
Change-Id: Ibb2fa2f7460d1a1f1e721242025e382734c204c6
|