Searched hist:"10 d13b28c22a2b5c27b904c783658442c37d9c08" (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/arm/kernel/ |
| H A D | kern.ld.S | 10d13b28c22a2b5c27b904c783658442c37d9c08 Tue May 16 09:09:11 UTC 2017 Etienne Carriere <etienne.carriere@linaro.org> core: exclusive writable/executable attribute in core mapping
Make executable memory non-writable and writable memory no-executable.
Effective upon CFG_CORE_RWDATA_NOEXEC=y. Default configuration enables
this directive.
If CFG_CORE_RWDATA_NOEXEC is enabled, the read-only sections are
mapped read-only/executable while the read/write memories are mapped
read/write/not-executable. Potential 4KB of secure RAM wasted since the
page alignment between unpaged text/rodata and unpaged read/write data.
If CFG_CORE_RWDATA_NOEXEC not disabled, all text/rodata/data/... sections
of the core are mapped read/write/executable.
Both code and rodata and mapped together without alignment constraint.
Hence define all "ro" are inside the "rx" relate area:
__vcore_init_ro_size = 0 or init "ro" effective size.
As init sections are mapped read-only, core won't be able to fill
trailing content of the init last page. Hence __init_end and __init_size
are page aligned.
Core must premap all physical memory as readable to allow move of
has tables to the allocated buffer during core inits.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_armv8)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
|
| /optee_os/core/arch/arm/ |
| H A D | arm.mk | 10d13b28c22a2b5c27b904c783658442c37d9c08 Tue May 16 09:09:11 UTC 2017 Etienne Carriere <etienne.carriere@linaro.org> core: exclusive writable/executable attribute in core mapping
Make executable memory non-writable and writable memory no-executable.
Effective upon CFG_CORE_RWDATA_NOEXEC=y. Default configuration enables
this directive.
If CFG_CORE_RWDATA_NOEXEC is enabled, the read-only sections are
mapped read-only/executable while the read/write memories are mapped
read/write/not-executable. Potential 4KB of secure RAM wasted since the
page alignment between unpaged text/rodata and unpaged read/write data.
If CFG_CORE_RWDATA_NOEXEC not disabled, all text/rodata/data/... sections
of the core are mapped read/write/executable.
Both code and rodata and mapped together without alignment constraint.
Hence define all "ro" are inside the "rx" relate area:
__vcore_init_ro_size = 0 or init "ro" effective size.
As init sections are mapped read-only, core won't be able to fill
trailing content of the init last page. Hence __init_end and __init_size
are page aligned.
Core must premap all physical memory as readable to allow move of
has tables to the allocated buffer during core inits.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_armv8)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
|
| /optee_os/core/arch/arm/mm/ |
| H A D | core_mmu.c | 10d13b28c22a2b5c27b904c783658442c37d9c08 Tue May 16 09:09:11 UTC 2017 Etienne Carriere <etienne.carriere@linaro.org> core: exclusive writable/executable attribute in core mapping
Make executable memory non-writable and writable memory no-executable.
Effective upon CFG_CORE_RWDATA_NOEXEC=y. Default configuration enables
this directive.
If CFG_CORE_RWDATA_NOEXEC is enabled, the read-only sections are
mapped read-only/executable while the read/write memories are mapped
read/write/not-executable. Potential 4KB of secure RAM wasted since the
page alignment between unpaged text/rodata and unpaged read/write data.
If CFG_CORE_RWDATA_NOEXEC not disabled, all text/rodata/data/... sections
of the core are mapped read/write/executable.
Both code and rodata and mapped together without alignment constraint.
Hence define all "ro" are inside the "rx" relate area:
__vcore_init_ro_size = 0 or init "ro" effective size.
As init sections are mapped read-only, core won't be able to fill
trailing content of the init last page. Hence __init_end and __init_size
are page aligned.
Core must premap all physical memory as readable to allow move of
has tables to the allocated buffer during core inits.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_armv8)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
|