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| /optee_os/core/arch/riscv/plat-virt/ |
| H A D | conf.mk | 10b2f530eefb09b78df5cd4e26fb41374e25a53d Fri Aug 30 01:54:04 UTC 2024 Alvin Chang <alvinga@andestech.com> riscv: plat-virt: Set CFG_BOOT_SYNC_CPU=n
On RISC-V QEMU virt platform, OP-TEE OS runs as S-mode. There is a
secure monitor runs as M-mode and controls the hart state of the
secondary CPUs in SMP system (e.g., by SBI HSM extension) during OP-TEE
OS secondary CPUs booting.
Thus, RISC-V virt platform does not need CFG_BOOT_SYNC_CPU.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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