Searched hist:"0 ed8b4bffc31e52facf27445503ea668e7ba3dc2" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/versal/ |
| H A D | plat_psci.c | 0ed8b4bffc31e52facf27445503ea668e7ba3dc2 Mon Oct 14 04:16:03 UTC 2024 Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> fix(versal): explicitly check operators precedence
This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.
Change-Id: I86bbbd4fe86be131a9e9775095d971d76eb956e3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
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| H A D | bl31_versal_setup.c | 0ed8b4bffc31e52facf27445503ea668e7ba3dc2 Mon Oct 14 04:16:03 UTC 2024 Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> fix(versal): explicitly check operators precedence
This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.
Change-Id: I86bbbd4fe86be131a9e9775095d971d76eb956e3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
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