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/rk3399_rockchip-uboot/board/altera/cyclone5-socdk/qts/
H A Dsdram_config.h0db1ac47ee1e88e3d3784bcdb3a0e1ea277419cc Wed Sep 21 02:25:57 UTC 2016 Chin Liang See <clsee@altera.com> arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
/rk3399_rockchip-uboot/board/altera/arria5-socdk/qts/
H A Dsdram_config.h0db1ac47ee1e88e3d3784bcdb3a0e1ea277419cc Wed Sep 21 02:25:57 UTC 2016 Chin Liang See <clsee@altera.com> arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>