Searched hist:"0 d3972cfcd6dff18d110d2ee01ad99e3623bfd45" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | fsl_ddr_gen4.c | 0d3972cfcd6dff18d110d2ee01ad99e3623bfd45 Wed Jan 06 03:26:51 UTC 2016 Shengzhou Liu <Shengzhou.Liu@freescale.com> fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | config.h | 0d3972cfcd6dff18d110d2ee01ad99e3623bfd45 Wed Jan 06 03:26:51 UTC 2016 Shengzhou Liu <Shengzhou.Liu@freescale.com> fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|