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| /optee_os/core/arch/riscv/kernel/ |
| H A D | thread_optee_abi_rv.S | 0cbfd093fb225302a55a749bc8447274026cf0b9 Wed Oct 11 02:21:39 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Implement thread_vector_table for ABI and FIQ entries
Implement thread_vector_table which only includes entries for standard
ABI, fast ABI, and foreign interrupts. Most of code is referenced from
ARM architecture. The thread_vector_table will be registered into higher
privileged software, such as M-mode firmware. The higher privileged
software can jump(mret) to OP-TEE based on this vector table.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| H A D | asm-defines.c | 0cbfd093fb225302a55a749bc8447274026cf0b9 Wed Oct 11 02:21:39 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Implement thread_vector_table for ABI and FIQ entries
Implement thread_vector_table which only includes entries for standard
ABI, fast ABI, and foreign interrupts. Most of code is referenced from
ARM architecture. The thread_vector_table will be registered into higher
privileged software, such as M-mode firmware. The higher privileged
software can jump(mret) to OP-TEE based on this vector table.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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