"0c44e92445749f8b67f5730f29044babc6bd62cf" (history) in projects: optee_os

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/optee_os/core/arch/riscv/kernel/
H A D	entry.S	`0c44e92445749f8b67f5730f29044babc6bd62cf Sun May 11 16:05:35 UTC 2025 Yu-Chien Peter Lin <peter.lin@sifive.com> core: riscv: enable MMU earlier for secondary cores Enable MMU for secondary harts earlier to ensure proper access to symbols in ASLR virtual addresses. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Alvin Chang <alvinga@andestech.com>`