Searched hist:"0 b3d4273fa9a18de64ce457834724fe6471237d8" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/include/drivers/cadence/ |
| H A D | cdns_uart.h | 0b3d4273fa9a18de64ce457834724fe6471237d8 Fri Oct 06 08:24:17 UTC 2017 Michal Simek <michal.simek@xilinx.com> cadence: Change logic in uart driver
Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.
Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
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| /rk3399_ARM-atf/drivers/cadence/uart/aarch64/ |
| H A D | cdns_console.S | 0b3d4273fa9a18de64ce457834724fe6471237d8 Fri Oct 06 08:24:17 UTC 2017 Michal Simek <michal.simek@xilinx.com> cadence: Change logic in uart driver
Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.
Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
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