Searched hist:"0 aa98cd27e0262f2595670396dff25856d305a2e" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/include/kernel/ |
| H A D | thread_private_arch.h | 0aa98cd27e0262f2595670396dff25856d305a2e Tue Jul 18 06:36:59 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Fix width of status CSR
Since we also support RV64 with 64-bit register width, fix the width of
status CSR by declaring it as "unsigned long" and encoding it by general
bit-wise operations instead of invoking fixed-width API.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| /optee_os/core/arch/riscv/kernel/ |
| H A D | thread_arch.c | 0aa98cd27e0262f2595670396dff25856d305a2e Tue Jul 18 06:36:59 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Fix width of status CSR
Since we also support RV64 with 64-bit register width, fix the width of
status CSR by declaring it as "unsigned long" and encoding it by general
bit-wise operations instead of invoking fixed-width API.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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