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| H A D | rpi.h | 060f9bf57b1dc1f9260bc1b999d054141b87d7d2 Fri Jul 24 07:22:11 UTC 2015 Alexander Stein <alexanders83@web.de> ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
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