Home
last modified time | relevance | path

Searched +full:xusb +full:- +full:padctl (Results 1 – 25 of 45) sorted by relevance

12

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra124-xusb-padctl.txt1 Device tree binding for NVIDIA Tegra XUSB pad controller
4 NOTE: It turns out that this binding isn't an accurate description of the XUSB
7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.txt1 Device tree binding for NVIDIA Tegra XUSB pad controller
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dxusb-padctl.c2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
14 #include "../xusb-padctl-common.h"
16 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
56 "xusb",
95 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
96 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
97 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
98 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
[all …]
H A DMakefile2 # (C) Copyright 2013-2014
5 # SPDX-License-Identifier: GPL-2.0+
8 obj-$(CONFIG_SPL_BUILD) += cpu.o
10 obj-y += clock.o
11 obj-y += funcmux.o
12 obj-y += pinmux.o
13 obj-y += pmc.o
14 obj-y += xusb-padctl.o
15 obj-y += ../xusb-padctl-common.o
18 obj-$(CONFIG_ARMV7_NONSEC) += psci.o
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.txt5 the Tegra XUSB pad controller.
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
15 registers and XUSB IPFS registers.
16 - reg-names: Must contain the following entries:
[all …]
H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC)
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/tegra/fuse/
H A Dfuse-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
44 if (WARN_ON(!fuse->base)) in tegra30_fuse_read_early()
47 return readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read_early()
55 err = clk_prepare_enable(fuse->clk); in tegra30_fuse_read()
57 dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err); in tegra30_fuse_read()
61 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read()
63 clk_disable_unprepare(fuse->clk); in tegra30_fuse_read()
92 fuse->read_early = tegra30_fuse_read_early; in tegra30_fuse_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dxusb-padctl.c2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
14 #include "../xusb-padctl-common.h"
18 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
35 "xusb",
37 "pcie-x1",
38 "pcie-x4",
75 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
76 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
[all …]
H A DMakefile2 # (C) Copyright 2013-2015
5 # SPDX-License-Identifier: GPL-2.0+
8 obj-y += clock.o
9 obj-y += funcmux.o
10 obj-y += pinmux.o
11 obj-y += xusb-padctl.o
12 obj-y += ../xusb-padctl-common.o
/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
13 #include <linux/phy/tegra/xusb.h>
22 #include "xusb.h"
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
[all …]
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
18 #include "xusb.h"
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
31 /* XUSB PADCTL registers */
144 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra186_xusb_padctl() argument
146 return container_of(padctl, struct tegra186_xusb_padctl, base); in to_tegra186_xusb_padctl()
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
[all …]
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "xusb.h"
220 to_tegra124_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra124_xusb_padctl() argument
222 return container_of(padctl, struct tegra124_xusb_padctl, base); in to_tegra124_xusb_padctl()
225 static int tegra124_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) in tegra124_xusb_padctl_enable() argument
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include "xusb.h"
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
254 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra210_xusb_padctl() argument
256 return container_of(padctl, struct tegra210_xusb_padctl, base); in to_tegra210_xusb_padctl()
259 /* must be called under padctl->lock */
260 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_enable() argument
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
12 #include "xusb-padctl-common.h"
18 if (phy && phy->ops && phy->ops->prepare) in tegra_xusb_phy_prepare()
19 return phy->ops->prepare(phy); in tegra_xusb_phy_prepare()
21 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_prepare()
26 if (phy && phy->ops && phy->ops->enable) in tegra_xusb_phy_enable()
27 return phy->ops->enable(phy); in tegra_xusb_phy_enable()
29 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_enable()
[all …]
H A Dxusb-padctl-common.h2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/arch-tegra/xusb-padctl.h>
40 struct tegra_xusb_padctl *padctl; member
86 extern struct tegra_xusb_padctl padctl;
88 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, in padctl_readl() argument
91 return readl(padctl->regs.start + offset); in padctl_readl()
94 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, in padctl_writel() argument
97 writel(value, padctl->regs.start + offset); in padctl_writel()
H A Dxusb-padctl-dummy.c4 * SPDX-License-Identifier: GPL-2.0
10 #include <asm/arch-tegra/xusb-padctl.h>
19 return -ENOSYS; in tegra_xusb_phy_prepare()
24 return -ENOSYS; in tegra_xusb_phy_enable()
29 return -ENOSYS; in tegra_xusb_phy_disable()
34 return -ENOSYS; in tegra_xusb_phy_unprepare()
H A DMakefile2 # (C) Copyright 2010-2015 Nvidia Corporation.
4 # (C) Copyright 2000-2008
7 # SPDX-License-Identifier: GPL-2.0+
12 obj-y += spl.o
13 obj-y += cpu.o
15 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
18 obj-y += ap.o
19 obj-y += board.o board2.o
20 obj-y += cache.o
21 obj-y += clock.o
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra186-p2771-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra186-p3310.dtsi"
11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
14 power-monitor@42 {
17 #address-cells = <1>;
18 #size-cells = <0>;
23 shunt-resistor-micro-ohms = <20000>;
[all …]
H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
34 hvddio-pex-supply = <&vdd_1v8>;
35 dvddio-pex-supply = <&vdd_pex_1v05>;
[all …]
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
13 interrupt-parent = <&lic>;
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20 #include "../pinctrl-utils.h"
93 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, in padctl_writel() argument
96 writel(value, padctl->regs + offset); in padctl_writel()
99 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, in padctl_readl() argument
102 return readl(padctl->regs + offset); in padctl_readl()
107 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); in tegra_xusb_padctl_get_groups_count() local
109 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
115 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); in tegra_xusb_padctl_get_group_name() local
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/host/
H A Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
19 #include <linux/phy/tegra/xusb.h>
235 struct tegra_xusb_padctl *padctl; member
280 return readl(tegra->fpci_base + offset); in fpci_readl()
286 writel(value, tegra->fpci_base + offset); in fpci_writel()
291 return readl(tegra->ipfs_base + offset); in ipfs_readl()
297 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
324 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()
338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra210-p2371-2180.dts1 /dts-v1/;
6 model = "NVIDIA P2371-2180";
7 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
10 stdout-path = &uarta;
24 pcie-controller@01003000 {
36 padctl@7009f000 {
37 pinctrl-0 = <&padctl_default>;
38 pinctrl-names = "default";
41 xusb {
42 nvidia,lanes = "otg-1", "otg-2";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dxusb-padctl.h7 * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
10 * The type of PHY varies between SoC generations. Typically there are XUSB,
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]

12