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/OK3568_Linux_fs/kernel/sound/hda/
H A Dhdac_controller.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio controller helpers
19 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", in azx_clear_corbrp()
29 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", in azx_clear_corbrp()
40 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
41 * @bus: HD-audio core bus
45 WARN_ON_ONCE(!bus->rb.area); in snd_hdac_bus_init_cmd_io()
47 spin_lock_irq(&bus->reg_lock); in snd_hdac_bus_init_cmd_io()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Generic Binding
10 - Ulf Hansson <ulf.hansson@linaro.org>
17 It is possible to assign a fixed index mmcN to an MMC host controller
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
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H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: "mmc-controller.yaml"
16 The Enhanced Secure Digital Host Controller on Freescale i.MX family
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
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H A Dsamsung,s3cmci.txt1 * Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings
3 Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface
7 mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller
11 - compatible: should be one of the following
12 - "samsung,s3c2410-sdi": for controllers compatible with s3c2410
13 - "samsung,s3c2412-sdi": for controllers compatible with s3c2412
14 - "samsung,s3c2440-sdi": for controllers compatible with s3c2440
15 - reg: register location and length
16 - interrupts: mmc controller interrupt
17 - clocks: Should reference the controller clock
[all …]
H A Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
3 The Enhanced Secure Digital Host Controller provides an interface
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
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H A Dk3-dw-mshc.txt2 Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
10 extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
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H A Dimg-dw-mshc.txt2 Host Controller
4 The Synopsys designware mobile storage host controller is used to interface
6 differences between the core Synopsys dw mshc controller properties described
7 by synopsys-dw-mshc.txt and the properties used by the Imagination specific
8 extensions to the Synopsys Designware Mobile Storage Host Controller.
13 - "img,pistachio-dw-mshc": for Pistachio SoCs
18 compatible = "img,pistachio-dw-mshc";
23 clock-names = "biu", "ciu";
25 fifo-depth = <0x20>;
26 bus-width = <4>;
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H A Datmel-hsmci.txt3 This controller on atmel products provides an interface for MMC, SD and SDIO
7 by mmc.txt and the properties used by the atmel-mci driver.
12 - compatible: should be "atmel,hsmci"
13 - #address-cells: should be one. The cell is the slot id.
14 - #size-cells: should be zero.
15 - at least one slot node
16 - clock-names: tuple listing input clock names.
18 - clocks: phandles to input clocks.
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/platform_data/
H A Dmmc-esdhc-imx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
13 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
14 ESDHC_WP_GPIO, /* external gpio pin for WP */
18 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
19 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
25 * struct esdhc_platform_data - platform data for esdhc on i.MX
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
H A Dbrcm,brcmnand.txt1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
5 registers and for its data input/output buffer. On some SoCs, this controller is
9 This controller was originally designed for STB SoCs (BCM7xxx) but is now
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
[all …]
H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs NAND controller devicetree bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
18 - ingenic,jz4740-nand
19 - ingenic,jz4725b-nand
20 - ingenic,jz4780-nand
24 - description: Bank number, offset and size of first attached NAND chip
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/nand/
H A Dnvidia,tegra20-nand.txt2 ----------
5 U-Boot. There should not be Linux-specific or U-Boot specific binding, just
12 - compatible : Should be "manufacturer,device", "nand-flash"
14 This node should sit inside its controller.
17 Nvidia NAND Controller
18 ----------------------
20 The device node for a NAND flash controller is as follows:
24 nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
26 nvidia,nand-width : bus width of the NAND device in bits
28 - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
35 mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6qdl-rex.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 stdout-path = &uart1;
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "regulator-fixed";
24 regulator-name = "3P3V";
25 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx50-kobo-aura.dts1 // SPDX-License-Identifier: GPL-2.0+
4 // The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
15 stdout-path = "serial1:115200n8";
23 gpio-leds {
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_leds>;
31 panic-indicator;
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H A Dkirkwood-pogoplug-series-4.dts1 // SPDX-License-Identifier: GPL-2.0
3 * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
10 /dts-v1/;
13 #include "kirkwood-6192.dtsi"
14 #include <dt-bindings/input/linux-event-codes.h>
18 compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
27 stdout-path = "uart0:115200n8";
31 compatible = "gpio-keys";
32 #address-cells = <1>;
33 #size-cells = <0>;
[all …]
H A Dimx6sx-sabreauto.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
11 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_led>;
26 linux,default-trigger = "heartbeat";
30 vcc_sd3: regulator-vcc-sd3 {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
[all …]
/OK3568_Linux_fs/u-boot/board/imx31_phycore/
H A Dimx31_phycore.c5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #include <asm/mach-types.h>
21 /* dram_init must store complete ramsize in gd->ram_size */ in dram_init()
22 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, in dram_init()
30 gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ in board_init()
31 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ in board_init()
40 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ in board_early_init_f()
48 /* CS1: Network Controller */ in board_early_init_f()
50 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ in board_early_init_f()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx6sx-sabreauto.dts9 /dts-v1/;
15 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "regulator-fixed";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_vcc_sd3>;
31 regulator-name = "VCC_SD3";
32 regulator-min-microvolt = <3000000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/net/ti-dp83867.h>
10 #include <dt-bindings/mux/ti-serdes.h>
14 stdout-path = "serial2:115200n8";
20 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
21 pinctrl-single,pins = <
37 mcu_mdio_pins_default: mcu-mdio1-pins-default {
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]
/OK3568_Linux_fs/kernel/drivers/bus/mhi/core/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
59 [MHI_PM_STATE_M3_ENTER] = "M?->M3",
61 [MHI_PM_STATE_M3_EXIT] = "M3->M0",
84 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; in serial_number_show()
87 mhi_cntrl->serial_number); in serial_number_show()
96 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; in oem_pk_hash_show()
99 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++) in oem_pk_hash_show()
[all …]
/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright © 2010-2015 Broadcom Corporation
31 * This flag controls if WP stays on between erase/write commands to mitigate
83 /* 512B flash cache in the NAND controller HW */
95 /* Controller feature flags */
109 struct nand_hw_control controller; member
121 /* Some SoCs have a gateable clock for the controller */
129 /* List of NAND hosts (one for each chip-select) */
135 /* in-memory cache of the FLASH_CACHE, used only for some commands */
138 /* Controller revision details */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/meson-g12a-gpio.h>
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
19 stdout-path = "serial0:115200n8";
27 adc-keys {
28 compatible = "adc-keys";
29 io-channels = <&saradc 2>;
30 io-channel-names = "buttons";
31 keyup-threshold-microvolt = <1710000>;
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