Searched +full:uniphier +full:- +full:system +full:- +full:cache (Results 1 – 25 of 53) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: UniPhier outer cache controller10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache11 controller system. All of them have a level 2 cache controller, and some12 have a level 3 cache controller as well.15 - Masahiro Yamada <yamada.masahiro@socionext.com>19 const: socionext,uniphier-system-cache[all …]
4 default "uniphier"14 prompt "UniPhier SoC select"18 bool "UniPhier LD4/sLD8 SoCs"22 bool "UniPhier Pro4 SoC"26 bool "UniPhier Pro5/PXs2/LD6b SoCs"30 bool "UniPhier V8 SoCs"38 bool "Enable UniPhier LD4 SoC support"43 bool "Enable UniPhier sLD8 SoC support"48 bool "Enable UniPhier Pro5 SoC support"53 bool "Enable UniPhier Pxs2 SoC support"[all …]
2 * Device Tree Source for UniPhier Pro5 SoC4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pro5";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";24 enable-method = "psci";[all …]
2 * Device Tree Source for UniPhier LD4 SoC4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-ld4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";23 enable-method = "psci";[all …]
2 * Device Tree Source for UniPhier sLD8 SoC4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-sld8";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";23 enable-method = "psci";[all …]
2 * Device Tree Source for UniPhier PXs2 SoC4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pxs2";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";24 enable-method = "psci";[all …]
2 * Device Tree Source for UniPhier Pro4 SoC4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pro4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";23 enable-method = "psci";[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier Pro5 SoC5 // Copyright (C) 2015-2016 Socionext Inc.9 compatible = "socionext,uniphier-pro5";10 #address-cells = <1>;11 #size-cells = <1>;14 #address-cells = <1>;15 #size-cells = <0>;19 compatible = "arm,cortex-a9";22 enable-method = "psci";[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier sLD8 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/uniphier-gpio.h>11 compatible = "socionext,uniphier-sld8";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier LD4 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/uniphier-gpio.h>11 compatible = "socionext,uniphier-ld4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier Pro4 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/uniphier-gpio.h>11 compatible = "socionext,uniphier-pro4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier PXs2 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/uniphier-gpio.h>9 #include <dt-bindings/thermal/thermal.h>12 compatible = "socionext,uniphier-pxs2";13 #address-cells = <1>;14 #size-cells = <1>;17 #address-cells = <1>;18 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Copyright (C) 2015-2016 Socionext Inc.7 #define pr_fmt(fmt) "uniphier: " fmt15 #include <asm/hardware/cache-uniphier.h>21 #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */23 #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */24 #define UNIPHIER_SSCC_ON BIT(0) /* enable cache */32 #define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */37 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */38 #define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */[all …]
1 # SPDX-License-Identifier: GPL-2.017 A 32-bit RISC microprocessor based on the ARM7 processor core18 which has no memory control unit and cache.36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and53 A 32-bit RISC processor with 8KB cache or 4KB variants,69 A 32-bit RISC microprocessor based on the ARM9 processor core70 which has no memory control unit and cache.147 instruction sequences for cache and TLB operations. Curiously,166 Branch Target Buffer, Unified TLB and cache line size 16.182 ARM940T is a member of the ARM9TDMI family of general-[all …]
1 # SPDX-License-Identifier: GPL-2.020 Low level power management driver for CCI400 cache coherent37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus42 bool "Baikal-T1 APB-bus driver"46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.53 errors counter. The counter and the APB-bus operations timeout can be57 bool "Baikal-T1 AXI-bus driver"61 AXI3-bus is the main communication bus connecting all high-speed62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI[all …]
2 * Copyright (C) 2012-2015 Panasonic Corporation3 * Copyright (C) 2015-2016 Socionext Inc.6 * SPDX-License-Identifier: GPL-2.0+12 #include <asm/system.h>18 * The UniPhier Boot ROM loads SPL code to the L2 cache.24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)43 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)65 mov r0, #-1 @ manager for all domains (No permission check)75 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)83 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.[all …]
... 2021.07/arch/arc/include/asm/cache.h u-boot-2021.07/arch/ ...
1 # SPDX-License-Identifier: GPL-2.0131 The ARM series is a line of low-power-consumption RISC chip designs133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer134 manufactured, but legacy ARM-based PC hardware remains popular in244 Patch phys-to-virt and virt-to-phys translation functions at246 kernel in system memory.248 This can only be used with non-XIP MMU kernels where the base280 location of main memory in your system.291 menu "System Type"294 bool "MMU-based Paged Memory Management Support"[all …]