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Searched +full:uniphier +full:- +full:sd4hc (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
11 - Piotr Sroka <piotrs@cadence.com>
14 - $ref: mmc-controller.yaml
19 - enum:
20 - socionext,uniphier-sd4hc
21 - const: cdns,sd4hc
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Duniphier-ld11.dtsi2 * Device Tree Source for UniPhier LD11 SoC
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
35 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Duniphier-pxs3.dtsi2 * Device Tree Source for UniPhier PXs3 SoC
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
41 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Duniphier-ld20.dtsi2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
12 compatible = "socionext,uniphier-ld11";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
[all …]
H A Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
H A Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dsdhci-cadence.c5 * SPDX-License-Identifier: GPL-2.0+
17 /* HRS - Host Register Set (specific to Cadence) */
26 /* SRS - Slot Register Set (SDHCI-compatible) */
55 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
56 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
57 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
58 { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
59 { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
60 { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
61 { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include "sdhci-pltfm.h"
18 /* HRS - Host Register Set (specific to Cadence) */
38 /* SRS - Slot Register Set (SDHCI-compatible) */
56 * The tuned val register is 6 bit-wide, but not the whole of the range is
57 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
80 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
81 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
82 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
83 { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
[all …]