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/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt2712.c756 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
1099 "uart_sel", 20),
1101 "uart_sel", 21),
1103 "uart_sel", 22),
1105 "uart_sel", 23),
1132 "uart_sel", 9),
1134 "uart_sel", 11),
1136 "uart_sel", 12),
1138 "uart_sel", 14),
1140 "uart_sel", 15),
[all …]
H A Dclk-mt6797.c339 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
483 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
484 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
485 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
486 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
H A Dclk-mt8183.c570 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
849 "uart_sel", 22),
851 "uart_sel", 23),
853 "uart_sel", 24),
855 "uart_sel", 25),
H A Dclk-mt6779.c684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
923 "uart_sel", 22),
925 "uart_sel", 23),
927 "uart_sel", 24),
929 "uart_sel", 25),
H A Dclk-mt8135.c373 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
506 "uart_sel",
H A Dclk-mt2701.c505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
872 "uart_sel",
H A Dclk-mt6765.c140 FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
H A Dclk-mt8173.c553 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
721 "uart_sel",
H A Dclk-mt7622.c535 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
H A Dclk-mt7629.c505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx35.c66 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, enumerator
139 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
140 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in _mx35_clocks_init()
H A Dclk-imx6sll.c209 …hws[IMX6SLL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE… in imx6sll_clocks_init()
229 hws[IMX6SLL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); in imx6sll_clocks_init()
H A Dclk-imx6sl.c321 …hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sel… in imx6sl_clocks_init()
360 …hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", b… in imx6sl_clocks_init()
H A Dclk-imx5.c157 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, in mx5_clocks_common_init()
159 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); in mx5_clocks_common_init()
H A Dclk-imx6ul.c258 …hws[IMX6UL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(… in imx6ul_clocks_init()
301 hws[IMX6UL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); in imx6ul_clocks_init()
H A Dclk-imx6sx.c288 …hws[IMX6SX_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, … in imx6sx_clocks_init()
329 …hws[IMX6SX_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", bas… in imx6sx_clocks_init()
H A Dclk-imx6q.c624 …hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(ua… in imx6q_clocks_init()
723 …hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24… in imx6q_clocks_init()
/OK3568_Linux_fs/u-boot/board/freescale/ls1046ardb/
H A Dcpld.c105 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); in cpld_dump_regs()
H A Dcpld.h24 u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ member
/OK3568_Linux_fs/u-boot/board/freescale/ls1043ardb/
H A Dcpld.c112 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); in cpld_dump_regs()
H A Dcpld.h23 u8 uart_sel; /* 0x9 - */ member
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dimx35-clock.yaml32 uart_sel 13
/OK3568_Linux_fs/u-boot/board/samsung/goni/
H A Dlowlevel_init.S407 /* UART_SEL GPK0[5] at S5PC100 */
429 /* UART_SEL MP0_5[7] at S5PC110 */
/OK3568_Linux_fs/u-boot/board/samsung/trats/
H A Dtrats.c389 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ in exynos_uart_init()
390 gpio_request(EXYNOS4_GPIO_Y47, "uart_sel"); in exynos_uart_init()