Home
last modified time | relevance | path

Searched full:uart_div (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/serial/
H A Dserial_intel_mid.c15 * UART clock = XTAL * UART_MUL / UART_DIV
23 #define UART_DIV 0x38 macro
48 mid_writel(plat, UART_DIV, 125); in mid_serial_probe()
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx35.c66 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, enumerator
140 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in _mx35_clocks_init()
207 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); in _mx35_clocks_init()
208 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); in _mx35_clocks_init()
209 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); in _mx35_clocks_init()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3308.c112 u32 uart_div[5] = {15, 15, 15, 15, 15}; in rkdclk_init() local
395 uart_div[UART_INFO_ID(ddr_gd.head_info.g_uart_info)] = 0; in rkdclk_init()
400 uart_div[0] << CLK_UART0_DIV_CON_SHIFT); in rkdclk_init()
403 uart_div[1] << CLK_UART1_DIV_CON_SHIFT); in rkdclk_init()
406 uart_div[2] << CLK_UART2_DIV_CON_SHIFT); in rkdclk_init()
409 uart_div[3] << CLK_UART3_DIV_CON_SHIFT); in rkdclk_init()
412 uart_div[4] << CLK_UART4_DIV_CON_SHIFT); in rkdclk_init()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dimx35-clock.yaml33 uart_div 14
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dwm0010.c64 u32 uart_div; member