Home
last modified time | relevance | path

Searched full:typ (Results 1 – 25 of 110) sorted by relevance

12345

/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Ddisplay.c31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
33 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
34 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
35 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
36 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
66 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, in update_display_mode()
69 writel(((timing->vback_porch.typ - vref_to_sync) << 16) | in update_display_mode()
70 timing->hback_porch.typ, &disp_ctrl->disp.back_porch); in update_display_mode()
[all …]
H A Dsor.c639 vtotal = timing->vsync_len.typ + timing->vback_porch.typ + in tegra_dc_sor_config_panel()
640 timing->vactive.typ + timing->vfront_porch.typ; in tegra_dc_sor_config_panel()
641 htotal = timing->hsync_len.typ + timing->hback_porch.typ + in tegra_dc_sor_config_panel()
642 timing->hactive.typ + timing->hfront_porch.typ; in tegra_dc_sor_config_panel()
648 vsync_end = timing->vsync_len.typ - 1; in tegra_dc_sor_config_panel()
649 hsync_end = timing->hsync_len.typ - 1; in tegra_dc_sor_config_panel()
654 vblank_end = vsync_end + timing->vback_porch.typ; in tegra_dc_sor_config_panel()
655 hblank_end = hsync_end + timing->hback_porch.typ; in tegra_dc_sor_config_panel()
660 vblank_start = vblank_end + timing->vactive.typ; in tegra_dc_sor_config_panel()
661 hblank_start = hblank_end + timing->hactive.typ; in tegra_dc_sor_config_panel()
H A Ddp.c510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
514 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
518 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, in tegra_dc_dp_calc_config()
519 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
521 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
601 num_symbols_per_line = (timing->hactive.typ * in tegra_dc_dp_calc_config()
622 link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ + in tegra_dc_dp_calc_config()
623 timing->hfront_porch.typ + timing->hsync_len.typ - 7) * in tegra_dc_dp_calc_config()
624 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
639 link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25) in tegra_dc_dp_calc_config()
[all …]
/OK3568_Linux_fs/kernel/include/linux/mlx5/
H A Ddevice.h49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) argument
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) argument
51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) argument
52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) argument
53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) argument
54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) argument
55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf… argument
56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1… argument
57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) argument
58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) argument
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/sunxi/
H A Dlcdc.c20 delay = mode->vfront_porch.typ + mode->vsync_len.typ + in lcdc_get_clk_delay()
21 mode->vback_porch.typ; in lcdc_get_clk_delay()
90 writel(SUNXI_LCDC_X(mode->hactive.typ) | in lcdc_tcon0_mode_set()
91 SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active); in lcdc_tcon0_mode_set()
93 bp = mode->hsync_len.typ + mode->hback_porch.typ; in lcdc_tcon0_mode_set()
94 total = mode->hactive.typ + mode->hfront_porch.typ + bp; in lcdc_tcon0_mode_set()
98 bp = mode->vsync_len.typ + mode->vback_porch.typ; in lcdc_tcon0_mode_set()
99 total = mode->vactive.typ + mode->vfront_porch.typ + bp; in lcdc_tcon0_mode_set()
104 writel(SUNXI_LCDC_X(mode->hsync_len.typ) | in lcdc_tcon0_mode_set()
105 SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync); in lcdc_tcon0_mode_set()
[all …]
H A Dsunxi_de2.c78 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); in sunxi_de2_mode_set()
169 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch); in sunxi_de2_mode_set()
217 uc_priv->xsize = timing.hactive.typ; in sunxi_de2_init()
218 uc_priv->ysize = timing.vactive.typ; in sunxi_de2_init()
/OK3568_Linux_fs/kernel/fs/freevxfs/
H A Dvxfs_bmap.c44 vxfs_typdump(struct vxfs_typed *typ) in vxfs_typdump() argument
46 printk(KERN_DEBUG "type=%Lu ", typ->vt_hdr >> VXFS_TYPED_TYPESHIFT); in vxfs_typdump()
47 printk("offset=%Lx ", typ->vt_hdr & VXFS_TYPED_OFFSETMASK); in vxfs_typdump()
48 printk("block=%x ", typ->vt_block); in vxfs_typdump()
49 printk("size=%x\n", typ->vt_size); in vxfs_typdump()
139 struct vxfs_typed *typ; in vxfs_bmap_indir() local
147 typ = ((struct vxfs_typed *)bp->b_data) + in vxfs_bmap_indir()
149 off = fs64_to_cpu(sbi, typ->vt_hdr) & VXFS_TYPED_OFFSETMASK; in vxfs_bmap_indir()
156 switch ((u_int32_t)(fs64_to_cpu(sbi, typ->vt_hdr) >> in vxfs_bmap_indir()
160 fs32_to_cpu(sbi, typ->vt_block), in vxfs_bmap_indir()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Datmel_lcdfb.c135 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
141 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
142 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
165 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; in atmel_fb_init()
166 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; in atmel_fb_init()
167 value |= timing->vfront_porch.typ; in atmel_fb_init()
173 value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET; in atmel_fb_init()
174 value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET; in atmel_fb_init()
175 value |= (timing->hback_porch.typ - 1); in atmel_fb_init()
179 value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET; in atmel_fb_init()
[all …]
H A Ddw_hdmi.c397 hbl = edid->hback_porch.typ + edid->hfront_porch.typ + in hdmi_av_composer()
398 edid->hsync_len.typ; in hdmi_av_composer()
399 vbl = edid->vback_porch.typ + edid->vfront_porch.typ + in hdmi_av_composer()
400 edid->vsync_len.typ; in hdmi_av_composer()
428 hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1); in hdmi_av_composer()
429 hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0); in hdmi_av_composer()
432 hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1); in hdmi_av_composer()
433 hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0); in hdmi_av_composer()
443 hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1); in hdmi_av_composer()
444 hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0); in hdmi_av_composer()
[all …]
H A Datmel_hlcdfb.c326 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
327 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
386 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1); in atmel_hlcdc_init()
387 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1); in atmel_hlcdc_init()
390 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); in atmel_hlcdc_init()
391 value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1); in atmel_hlcdc_init()
394 value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1); in atmel_hlcdc_init()
395 value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1); in atmel_hlcdc_init()
399 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1); in atmel_hlcdc_init()
400 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1); in atmel_hlcdc_init()
[all …]
H A Dtegra.c111 writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); in update_display_mode()
112 writel(dt->hback_porch.typ | dt->vback_porch.typ << 16, in update_display_mode()
114 writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16, in update_display_mode()
116 writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); in update_display_mode()
366 priv->width = timing->hactive.typ; in tegra_lcd_ofdata_to_platdata()
367 priv->height = timing->vactive.typ; in tegra_lcd_ofdata_to_platdata()
368 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_ofdata_to_platdata()
/OK3568_Linux_fs/kernel/drivers/isdn/hardware/mISDN/
H A Diohelper.h65 #define IOFUNC_MEMIO(name, hws, typ, adr) \ argument
68 return readb(((typ *)hw->adr) + off); \
72 writeb(val, ((typ *)hw->adr) + off); \
77 *dp++ = readb(((typ *)hw->adr) + off); \
82 writeb(*dp++, ((typ *)hw->adr) + off); \
85 #define ASSIGN_FUNC(typ, name, dest) do { \ argument
86 dest.read_reg = &Read##name##_##typ; \
87 dest.write_reg = &Write##name##_##typ; \
88 dest.read_fifo = &ReadFiFo##name##_##typ; \
89 dest.write_fifo = &WriteFiFo##name##_##typ; \
[all …]
/OK3568_Linux_fs/kernel/drivers/video/
H A Dvideomode.c16 vm->pixelclock = dt->pixelclock.typ; in videomode_from_timing()
17 vm->hactive = dt->hactive.typ; in videomode_from_timing()
18 vm->hfront_porch = dt->hfront_porch.typ; in videomode_from_timing()
19 vm->hback_porch = dt->hback_porch.typ; in videomode_from_timing()
20 vm->hsync_len = dt->hsync_len.typ; in videomode_from_timing()
22 vm->vactive = dt->vactive.typ; in videomode_from_timing()
23 vm->vfront_porch = dt->vfront_porch.typ; in videomode_from_timing()
24 vm->vback_porch = dt->vback_porch.typ; in videomode_from_timing()
25 vm->vsync_len = dt->vsync_len.typ; in videomode_from_timing()
H A Dof_display_timing.c23 * a range consisting of min/typ/max. This function helps handling this
39 ret = of_property_read_u32(np, name, &result->typ); in parse_timing_property()
40 result->min = result->typ; in parse_timing_property()
41 result->max = result->typ; in parse_timing_property()
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_vop.c42 u32 hactive = edid->hactive.typ; in rkvop_enable()
43 u32 vactive = edid->vactive.typ; in rkvop_enable()
48 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | in rkvop_enable()
49 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), in rkvop_enable()
146 u32 hactive = edid->hactive.typ; in rkvop_mode_set()
147 u32 vactive = edid->vactive.typ; in rkvop_mode_set()
148 u32 hsync_len = edid->hsync_len.typ; in rkvop_mode_set()
149 u32 hback_porch = edid->hback_porch.typ; in rkvop_mode_set()
150 u32 vsync_len = edid->vsync_len.typ; in rkvop_mode_set()
151 u32 vback_porch = edid->vback_porch.typ; in rkvop_mode_set()
[all …]
H A Drk_mipi.c92 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
93 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
94 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
95 + timing->hback_porch.typ + timing->hactive.typ in rk_mipi_dsi_enable()
96 + timing->hfront_porch.typ)); in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
98 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
99 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); in rk_mipi_dsi_enable()
100 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); in rk_mipi_dsi_enable()
/OK3568_Linux_fs/external/rknpu2/examples/3rdparty/opencv/opencv-linux-aarch64/include/opencv2/core/hal/
H A Dintrin.hpp229 #define CV_INTRIN_DEFINE_WIDE_INTRIN(typ, vtyp, short_typ, prefix, loadsfx) \ argument
230 inline vtyp vx_setall_##short_typ(typ v) { return prefix##_setall_##short_typ(v); } \
232 inline vtyp vx_##loadsfx(const typ* ptr) { return prefix##_##loadsfx(ptr); } \
233 … inline vtyp vx_##loadsfx##_aligned(const typ* ptr) { return prefix##_##loadsfx##_aligned(ptr); } \
234 inline vtyp vx_##loadsfx##_low(const typ* ptr) { return prefix##_##loadsfx##_low(ptr); } \
235 …inline vtyp vx_##loadsfx##_halves(const typ* ptr0, const typ* ptr1) { return prefix##_##loadsfx##_…
236 inline void vx_store(typ* ptr, const vtyp& v) { return v_store(ptr, v); } \
237 inline void vx_store_aligned(typ* ptr, const vtyp& v) { return v_store_aligned(ptr, v); }
239 #define CV_INTRIN_DEFINE_WIDE_LOAD_EXPAND(typ, wtyp, prefix) \ argument
240 inline wtyp vx_load_expand(const typ* ptr) { return prefix##_load_expand(ptr); }
[all …]
/OK3568_Linux_fs/external/rknpu2/examples/3rdparty/opencv/OpenCV-android-sdk/sdk/native/jni/include/opencv2/core/hal/
H A Dintrin.hpp229 #define CV_INTRIN_DEFINE_WIDE_INTRIN(typ, vtyp, short_typ, prefix, loadsfx) \ argument
230 inline vtyp vx_setall_##short_typ(typ v) { return prefix##_setall_##short_typ(v); } \
232 inline vtyp vx_##loadsfx(const typ* ptr) { return prefix##_##loadsfx(ptr); } \
233 … inline vtyp vx_##loadsfx##_aligned(const typ* ptr) { return prefix##_##loadsfx##_aligned(ptr); } \
234 inline vtyp vx_##loadsfx##_low(const typ* ptr) { return prefix##_##loadsfx##_low(ptr); } \
235 …inline vtyp vx_##loadsfx##_halves(const typ* ptr0, const typ* ptr1) { return prefix##_##loadsfx##_…
236 inline void vx_store(typ* ptr, const vtyp& v) { return v_store(ptr, v); } \
237 inline void vx_store_aligned(typ* ptr, const vtyp& v) { return v_store_aligned(ptr, v); }
239 #define CV_INTRIN_DEFINE_WIDE_LOAD_EXPAND(typ, wtyp, prefix) \ argument
240 inline wtyp vx_load_expand(const typ* ptr) { return prefix##_load_expand(ptr); }
[all …]
/OK3568_Linux_fs/external/rknpu2/examples/3rdparty/opencv/opencv-linux-armhf/include/opencv2/core/hal/
H A Dintrin.hpp229 #define CV_INTRIN_DEFINE_WIDE_INTRIN(typ, vtyp, short_typ, prefix, loadsfx) \ argument
230 inline vtyp vx_setall_##short_typ(typ v) { return prefix##_setall_##short_typ(v); } \
232 inline vtyp vx_##loadsfx(const typ* ptr) { return prefix##_##loadsfx(ptr); } \
233 … inline vtyp vx_##loadsfx##_aligned(const typ* ptr) { return prefix##_##loadsfx##_aligned(ptr); } \
234 inline vtyp vx_##loadsfx##_low(const typ* ptr) { return prefix##_##loadsfx##_low(ptr); } \
235 …inline vtyp vx_##loadsfx##_halves(const typ* ptr0, const typ* ptr1) { return prefix##_##loadsfx##_…
236 inline void vx_store(typ* ptr, const vtyp& v) { return v_store(ptr, v); } \
237 inline void vx_store_aligned(typ* ptr, const vtyp& v) { return v_store_aligned(ptr, v); }
239 #define CV_INTRIN_DEFINE_WIDE_LOAD_EXPAND(typ, wtyp, prefix) \ argument
240 inline wtyp vx_load_expand(const typ* ptr) { return prefix##_load_expand(ptr); }
[all …]
/OK3568_Linux_fs/yocto/poky/bitbake/lib/hashserv/
H A D__init__.py59 fields=" ".join("%s %s," % (name, typ) for name, typ, _ in definition),
124 (typ, a) = parse_address(addr)
125 if typ == ADDR_TYPE_UNIX:
137 (typ, a) = parse_address(addr)
138 if typ == ADDR_TYPE_UNIX:
149 (typ, a) = parse_address(addr)
150 if typ == ADDR_TYPE_UNIX:
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/panel/
H A Dpanel-timing.yaml57 of min, typ, max values.
83 description: min, typ, max number of pixels
96 description: min, typ, max number of pixels
109 description: min, typ, max number of pixels
122 description: min, typ, max number of lines
135 description: min, typ, max number of lines
148 description: min, typ, max number of lines
/OK3568_Linux_fs/kernel/drivers/infiniband/hw/mlx5/
H A Dqpc.c378 #define MBOX_ALLOC(mbox, typ) \ in modify_qp_mbox_alloc() argument
379 mbox_alloc(mbox, MLX5_ST_SZ_BYTES(typ##_in), MLX5_ST_SZ_BYTES(typ##_out)) in modify_qp_mbox_alloc()
381 #define MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid) \ in modify_qp_mbox_alloc() argument
383 MLX5_SET(typ##_in, in, opcode, _opcode); \ in modify_qp_mbox_alloc()
384 MLX5_SET(typ##_in, in, qpn, _qpn); \ in modify_qp_mbox_alloc()
385 MLX5_SET(typ##_in, in, uid, _uid); \ in modify_qp_mbox_alloc()
388 #define MOD_QP_IN_SET_QPC(typ, in, _opcode, _qpn, _opt_p, _qpc, _uid) \ in modify_qp_mbox_alloc() argument
390 MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid); \ in modify_qp_mbox_alloc()
391 MLX5_SET(typ##_in, in, opt_param_mask, _opt_p); \ in modify_qp_mbox_alloc()
392 memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc, \ in modify_qp_mbox_alloc()
/OK3568_Linux_fs/kernel/include/linux/platform_data/
H A Dadp8870.h119 u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
121 u8 l2_bright_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
123 u8 l3_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
125 u8 l4_indor_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
127 u8 l5_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
/OK3568_Linux_fs/kernel/drivers/scsi/snic/
H A Dsnic_disc.c35 snic_tgt_type_to_str(int typ) in snic_tgt_type_to_str() argument
37 return ((typ > SNIC_TGT_NONE && typ <= SNIC_TGT_SAN) ? in snic_tgt_type_to_str()
38 snic_tgt_type_str[typ] : "Unknown"); in snic_tgt_type_to_str()
274 tgt->tdata.typ = le16_to_cpu(tgtid->tgt_type); in snic_tgt_create()
286 switch (tgt->tdata.typ) { in snic_tgt_create()
312 tgt->id, snic_tgt_type_to_str(tgt->tdata.typ)); in snic_tgt_create()
398 u8 typ, cmpl_stat; in snic_report_tgt_cmpl_handler() local
405 snic_io_hdr_dec(&fwreq->hdr, &typ, &cmpl_stat, &cmnd_id, &hid, &ctx); in snic_report_tgt_cmpl_handler()
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dlnbh29.c35 /* Min: 13.188V, Typ: 13.667V, Max:14V */
37 /* Min: 18.158V, Typ: 18.817V, Max:19.475V */
116 /* Soft-start time (Vout 0V to 18V) is Typ. 6ms. */ in lnbh29_set_voltage()

12345