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Searched full:tx_clk (Results 1 – 25 of 46) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sunxi.c23 struct clk *tx_clk; member
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
53 ret = clk_prepare(gmac->tx_clk); in sun7i_gmac_init()
66 clk_disable(gmac->tx_clk); in sun7i_gmac_exit()
69 clk_unprepare(gmac->tx_clk); in sun7i_gmac_exit()
84 clk_disable(gmac->tx_clk); in sun7i_fix_speed()
87 clk_unprepare(gmac->tx_clk); in sun7i_fix_speed()
90 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_fix_speed()
[all …]
H A Ddwmac-intel-plat.c20 struct clk *tx_clk; member
37 rate = clk_get_rate(dwmac->tx_clk); in kmb_eth_fix_mac_speed()
57 ret = clk_set_rate(dwmac->tx_clk, rate); in kmb_eth_fix_mac_speed()
104 dwmac->tx_clk = NULL; in intel_eth_plat_probe()
115 dwmac->tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); in intel_eth_plat_probe()
116 if (IS_ERR(dwmac->tx_clk)) { in intel_eth_plat_probe()
117 ret = PTR_ERR(dwmac->tx_clk); in intel_eth_plat_probe()
121 clk_prepare_enable(dwmac->tx_clk); in intel_eth_plat_probe()
124 rate = clk_get_rate(dwmac->tx_clk); in intel_eth_plat_probe()
128 ret = clk_set_rate(dwmac->tx_clk, rate); in intel_eth_plat_probe()
[all …]
H A Ddwmac-sun8i.c60 * @tx_clk: reference to MAC TX clock
71 struct clk *tx_clk; member
560 ret = clk_prepare_enable(gmac->tx_clk); in sun8i_dwmac_init()
575 clk_disable_unprepare(gmac->tx_clk); in sun8i_dwmac_init()
1028 clk_disable_unprepare(gmac->tx_clk); in sun8i_dwmac_exit()
1152 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); in sun8i_dwmac_probe()
1153 if (IS_ERR(gmac->tx_clk)) { in sun8i_dwmac_probe()
1155 return PTR_ERR(gmac->tx_clk); in sun8i_dwmac_probe()
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1012a_serdes.c23 {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
24 {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
25 {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-clk-ccf.dtsi123 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
130 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
137 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
144 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
H A Dzynqmp.dtsi447 clock-names = "pclk", "hclk", "tx_clk";
459 clock-names = "pclk", "hclk", "tx_clk";
471 clock-names = "pclk", "hclk", "tx_clk";
483 clock-names = "pclk", "hclk", "tx_clk";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dmacb.txt27 Optional elements: 'tx_clk'
49 clock-names = "pclk", "hclk", "tx_clk";
H A Dqcom-emac.txt44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
H A Dintel,dwmac-plat.yaml42 - const: tx_clk
110 clock-names = "stmmaceth", "ptp_ref", "tx_clk";
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dssd2828.c124 * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet, in soft_spi_xfer_24bit_3wire()
125 * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs in soft_spi_xfer_24bit_3wire()
128 * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in in soft_spi_xfer_24bit_3wire()
377 * Pick the reference clock for PLL. If we know the exact 'tx_clk' in ssd2828_init()
H A Dssd2828.h46 * The SSD2828 has its own dedicated clock source 'tx_clk' (connected
50 * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
H A DKconfig323 int "SSD2828 TX_CLK frequency (in MHz)"
332 parallel LCD interface instead of TX_CLK as the PLL clock source.
/OK3568_Linux_fs/kernel/drivers/dma/xilinx/
H A Dxilinx_dma.c472 struct clk **tx_clk, struct clk **txs_clk,
489 * @tx_clk: DMA mm2s clock
507 struct clk *tx_clk; member
2562 struct clk **tx_clk, struct clk **rx_clk, in axidma_clk_init() argument
2573 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axidma_clk_init()
2574 if (IS_ERR(*tx_clk)) in axidma_clk_init()
2575 *tx_clk = NULL; in axidma_clk_init()
2591 err = clk_prepare_enable(*tx_clk); in axidma_clk_init()
2593 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axidma_clk_init()
2614 clk_disable_unprepare(*tx_clk); in axidma_clk_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Dmicrel.c534 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
538 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
620 u16 rx, tx, rx_clk, tx_clk; in ksz9031_config_rgmii_delay() local
626 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
632 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
638 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
644 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
675 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | in ksz9031_config_rgmii_delay()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/cadence/
H A Dmacb_main.c499 netdev_err(dev, "adjusting tx_clk failed.\n"); in macb_set_tx_clk()
652 macb_set_tx_clk(bp->tx_clk, speed, ndev); in macb_mac_link_up()
3610 struct clk **hclk, struct clk **tx_clk, in macb_clk_init() argument
3643 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); in macb_clk_init()
3644 if (IS_ERR(*tx_clk)) in macb_clk_init()
3645 return PTR_ERR(*tx_clk); in macb_clk_init()
3667 err = clk_prepare_enable(*tx_clk); in macb_clk_init()
3669 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in macb_clk_init()
3691 clk_disable_unprepare(*tx_clk); in macb_clk_init()
4219 struct clk **hclk, struct clk **tx_clk, in at91ether_clk_init() argument
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/stv0991/
H A Dclock.c33 /* Clock selection for ethernet tx_clk & rx_clk*/ in clock_setup()
/OK3568_Linux_fs/kernel/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c280 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */ in sja1105_mii_clocking_setup()
382 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
383 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ in sja1105_rgmii_cfg_pad_tx_config()
384 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dfsl_serdes.h145 TX_CLK, enumerator
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
H A Dmpc832x_mds.dts192 3 24 2 0 1 0 /* TX_CLK (CLK10) */
212 3 6 2 0 1 0 /* TX_CLK (CLK8) */
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi222 clock-names = "pclk", "hclk", "tx_clk";
233 clock-names = "pclk", "hclk", "tx_clk";
H A Dzynqmp.dtsi577 clock-names = "pclk", "hclk", "tx_clk";
591 clock-names = "pclk", "hclk", "tx_clk";
605 clock-names = "pclk", "hclk", "tx_clk";
619 clock-names = "pclk", "hclk", "tx_clk";
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmscc.c379 /* Reg20E2 - Update RGMII TX_Clk Skews. */ in vsc8531_config()
440 /* Reg20E2 - Update RGMII TX_Clk Skews. */ in vsc8541_config()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsocfpga_arria10_socdk.dtsi75 * for TX_CLK on Arria 10.
H A Dzynq-7000.dtsi239 clock-names = "pclk", "hclk", "tx_clk";
250 clock-names = "pclk", "hclk", "tx_clk";

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