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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
48 clock-names:
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/sun/
H A Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
43 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
50 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
51 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
76 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
77 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
78 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
[all …]
H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dampdu.c27 /* max number of mpdus in an ampdu */
29 /* max number of mpdus in an ampdu to a legacy */
31 /* max Tx ba window size (in pdu) */
33 /* default Tx ba window size (in pdu) */
37 /* max Rx ba window size (in pdu) */
39 /* max dur of tx ampdu (in msec) */
41 /* default tx retry limit */
43 /* default tx retry limit at reg rate */
49 /* max # of mpdus released at a time */
52 #define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
H A Dklondike.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
24 #address-cells = <1>;
25 #size-cells = <0>;
31 clock-frequency = <300000000>; /* Filled in by U-Boot */
32 timebase-frequency = <300000000>; /* Filled in by U-Boot */
33 i-cache-line-size = <32>;
[all …]
H A Dtaishan.dts13 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <1>;
20 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <800000000>; // 800MHz
38 timebase-frequency = <0>; // Filled in by zImage
39 i-cache-line-size = <50>;
40 d-cache-line-size = <50>;
[all …]
H A Dobs600.dts8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
[all …]
H A Dfsp2.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dhotfoot.dts4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
37 i-cache-line-size = <0x20>;
[all …]
H A Dmakalu.dts11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dbamboo.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
33 #address-cells = <1>;
34 #size-cells = <0>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
[all …]
H A Dsam440ep.dts16 /dts-v1/;
19 #address-cells = <2>;
20 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
[all …]
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
130 * struct st_i2c_timings - per-Mode tuning parameters
152 * struct st_i2c_client - client specific data
153 * @addr: 8-bit slave addr, including r/w bit
170 * struct st_i2c_dev - private data of the controller
181 * @busy: I2C transfer on-going
211 * compatible with some out-of-spec devices,
240 * Counter only counts up to 7 but fifo size is 8... in st_i2c_flush_rx_fifo()
[all …]
H A Di2c-qup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
77 /* Most significant word offset in FIFO port */
144 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
148 /* Max data length for each DATARD tags */
150 /* TAG length for DATA READ in RX FIFO */
160 * tx_tag_len: tx tag length for current block
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
166 * tx_fifo_data_pos: current byte number in TX FIFO word
[all …]
H A Di2c-pnx.c7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
38 int order; /* RX Bytes to order via TX */
84 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
85 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
86 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
87 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
88 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
89 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
90 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
91 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qup.txt3 The QUP core is an AHB slave that provides a common data path (an output FIFO
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Dsnps_udc_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
63 * slave mode: pending bytes in rx fifo after nyet,
76 /* set_rde -- Is used to control enabling of RX DMA. Problem is
79 * when OUT data reaches the fifo but no request was queued yet.
82 * in the FIFO (important for not blocking control traffic).
85 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 1 == timer function will look whether FIFO has data
90 static int set_rde = -1;
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/google/gve/
H A Dgve.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2019 Google, Inc.
10 #include <linux/dma-mapping.h>
27 /* 1 for management, 1 for rx, 1 for tx */
30 /* Numbers of gve tx/rx stats in stats report. */
37 /* Numbers of NIC tx/rx stats in stats report. */
75 /* An RX ring that contains a power-of-two sized desc and data ring. */
80 u64 rbytes; /* free-running bytes received */
81 u64 rpackets; /* free-running packets received */
82 u32 cnt; /* free-running total number of completed packets */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/can/m_can/
H A Dm_can.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
229 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
235 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
244 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
248 /* Tx Buffer Configuration(TXBC) */
254 /* Tx FIFO/Queue Status (TXFQS) */
263 /* Tx Buffer Element Size Configuration(TXESC) */
267 /* Tx Event FIFO Configuration (TXEFC) */
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/fm/
H A Dfm.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
37 align_mask = align - 1; in fm_muram_alloc()
42 muram[fm_idx].alloc += (align - off); in fm_muram_alloc()
45 size += (align - off); in fm_muram_alloc()
70 * fm_upload_ucode - Fman microcode upload worker function
82 out_be32(&imem->iadd, IRAM_IADD_AIE); in fm_upload_ucode()
85 out_be32(&imem->idata, (be32_to_cpu(ucode[i]))); in fm_upload_ucode()
88 out_be32(&imem->iadd, 0); in fm_upload_ucode()
89 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout) in fm_upload_ucode()
[all …]

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