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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
101 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
105 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
118 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
127 hw->init = &init; in meson8b_dwmac_register_clk()
129 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
135 struct device *dev = dwmac->dev; in meson8b_init_rgmii_tx_clk()
[all …]
H A Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
83 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
84 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
91 * configured, equals to (plat->variant->num_clks - 1) in default for all the case, in mt2712_set_interface()
94 plat->num_clks_to_config = plat->variant->num_clks - 1; in mt2712_set_interface()
97 switch (plat->phy_mode) { in mt2712_set_interface()
102 if (plat->rmii_clk_from_mac) in mt2712_set_interface()
103 plat->num_clks_to_config++; in mt2712_set_interface()
113 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
114 return -EINVAL; in mt2712_set_interface()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
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/OK3568_Linux_fs/kernel/drivers/video/backlight/
H A Dtdo24m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
45 #define CMD_NULL (-1)
92 CMD1(0xd1, 0x01), /* CKV timing control on/off */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
96 CMD1(0xd5, 0x14), /* ASW timing control (2) */
105 CMD1(0xd8, 0x01), /* CKV timing control on/off */
106 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
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/OK3568_Linux_fs/kernel/net/mac80211/
H A Dmesh_sync.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012, Pavel Zubarev <pavel.zubarev@gmail.com>
4 * Copyright 2011-2012, Marco Porsch <marco.porsch@s2005.tu-chemnitz.de>
5 * Copyright 2011-2012, cozybit Inc.
10 #include "driver-ops.h"
13 * which we do no TSF adjustment.
19 * introduced by TSF adjustment latency.
36 * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT
42 return (ie->mesh_config->meshconf_cap & in mesh_peer_tbtt_adjusting()
48 struct ieee80211_local *local = sdata->local; in mesh_sync_adjust_tsf()
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_display_helper.c4 * SPDX-License-Identifier: GPL-2.0+
21 unsigned long poly; /* polynomial exclusive-or pattern */ in rockchip_display_make_crc32_table()
25 /* make exclusive-or pattern from polynomial (0xedb88320L) */ in rockchip_display_make_crc32_table()
28 poly |= 1L << (31 - p[n]); in rockchip_display_make_crc32_table()
53 * drm_mode_max_resolution_filter - mark modes out of vop max resolution
62 for (i = 0; i < edid_data->modes; i++) { in drm_mode_max_resolution_filter()
63 if (edid_data->mode_buf[i].hdisplay > max_output->width || in drm_mode_max_resolution_filter()
64 edid_data->mode_buf[i].vdisplay > max_output->height) in drm_mode_max_resolution_filter()
65 edid_data->mode_buf[i].invalid = true; in drm_mode_max_resolution_filter()
74 if (mode->vrefresh > 0) { in drm_mode_vrefresh()
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
16 #include "sdhci-pltfm.h"
17 #include "sdhci-xenon.h"
86 * according to board actual timing.
117 /* Offset of Timing Adjust register */
127 /* Offset of Logic Timing Adjust register */
131 /* value in Logic Timing Adjustment register */
206 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
208 return -ENOMEM; in xenon_alloc_emmc_phy()
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H A Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
21 #include "sdhci-pltfm.h"
22 #include "sdhci-xenon.h"
41 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
42 return -ETIMEDOUT; in xenon_enable_internal_clk()
50 /* Set SDCLK-off-while-idle */
91 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
96 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
137 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
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H A Drenesas_sdhi_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
30 #include <linux/mmc/slot-gpio.h>
35 #include <linux/pinctrl/pinctrl-state.h>
87 struct mmc_host *mmc = host->mmc; in renesas_sdhi_clk_enable()
91 ret = clk_prepare_enable(priv->clk_cd); in renesas_sdhi_clk_enable()
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/OK3568_Linux_fs/external/rockit/mpi/sdk/include/
H A Drk_comm_venc.h1 /* GPL-2.0 WITH Linux-syscall-note OR Apache 2.0 */
414 /* RW; Range:[-1, 2147483647]; Number of frames received and encoded by the encoding channel,
415 0 is not supported, -1 is not limit recv pic num*/
454 …/* RW; Range:[0,2]; Conversion mode for inter-prediction&intra-prediction,0: trans4x4, trans8x8; 1…
458 …ScalingList8X8[64]; /* RW; Range:[1,255]; A quantization table for 8x8 inter-prediction*/
459 …ScalingList8X8[64]; /* RW; Range:[1,255]; A quantization table for 8x8 intra-prediction*/
460 /* RW; Range:[-12,12];default value: -6, see the H.264 protocol for the meaning*/
480 …RK_S32 slice_alpha_c0_offset_div2; /* RW; Range:[-6,+6]; see the H.264 protocol for t…
481 …RK_S32 slice_beta_offset_div2; /* RW; Range:[-6,+6]; see the H.264 protocol for t…
484 /* the param of the h264e vui timing info */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmeson8m2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/phydm/rtl8188e/
H A Dhal8188erateadaptive.c1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) Semiconductor - 2017 Realtek Corporation.
202 static u16 dynamic_tx_rpt_timing[6] = {0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /*200ms-120…
214 if (DM_RA_RATE_UP != p_ra_info->rate_direction) { in odm_ra_learn_bounding()
215 /* Check if previous RA adjustment trend as +++--- or ++++----*/ in odm_ra_learn_bounding()
216 …->rate_up_counter && p_ra_info->bounding_learning_time <= 10) || (4 == p_ra_info->rate_up_counter … in odm_ra_learn_bounding()
217 if (1 != p_ra_info->bounding_type) { in odm_ra_learn_bounding()
218 p_ra_info->bounding_type = 1; in odm_ra_learn_bounding()
219 p_ra_info->bounding_counter = 0; in odm_ra_learn_bounding()
221 p_ra_info->bounding_counter++; in odm_ra_learn_bounding()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlegacy/
H A D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
[all …]
/OK3568_Linux_fs/kernel/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include "tick-internal.h"
22 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
57 sftacc--; in clocks_calc_mult_shift()
64 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
76 /*[Clocksource internal variables]---------
86 * Name of the user-specified clocksource.
154 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); in __clocksource_unstable()
155 cs->flags |= CLOCK_SOURCE_UNSTABLE; in __clocksource_unstable()
159 * re-rate and re-select. in __clocksource_unstable()
[all …]
/OK3568_Linux_fs/kernel/drivers/iio/proximity/
H A Dvcnl3020.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define VCNL_PS_MOD_ADJ 0x8f /* Proximity Modulator Timing Adjustment */
36 #define VCNL_PS_OD BIT(3) /* start on-demand proximity
44 * struct vcnl3020_data - vcnl3020 specific data.
58 * struct vcnl3020_property - vcnl3020 property.
79 .name = "vishay,led-current-microamp",
90 rc = device_property_read_u32(data->dev, prop.name, &val); in vcnl3020_get_and_apply_property()
97 rc = regmap_write(data->regmap, prop.reg, val); in vcnl3020_get_and_apply_property()
99 dev_err(data->dev, "Error (%d) setting property (%s)\n", in vcnl3020_get_and_apply_property()
111 rc = regmap_read(data->regmap, VCNL_PROD_REV, &reg); in vcnl3020_init()
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/OK3568_Linux_fs/kernel/include/linux/
H A Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
73 * when an interrupt takes places versus a high speed, fine-grained
74 * timing source or cycle counter. Since it will be occurred on every
[all …]
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
22 * This driver configures the 2 16/32-bit count-up timers as follows:
29 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
33 * obtained from device tree. The pre-scaler of 32 is used.
54 * Setup the timers to use pre-scaling, using a fixed value for now that will
59 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
66 * struct ttc_timer - This definition defines local timer structure
104 * ttc_set_interval - Set the timer interval value
114 /* Disable the counter, set the counter value and re-enable counter */ in ttc_set_interval()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
59 * (access to non-DC registers will hang FPGA) */
196 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
198 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
279 /* native display timing*/
284 *_not_ related to the Reduced Blanking adjustment*/
292 /* this timing should be used only in tiled mode*/
297 Must be zero for wired displays and non-zero for
333 /* these timing might not work, least important*/
388 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dks0127.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
20 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
31 #include <media/v4l2-device.h>
258 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */ in init_reg_defaults()
259 table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */ in init_reg_defaults()
260 table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */ in init_reg_defaults()
261 table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */ in init_reg_defaults()
265 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */ in init_reg_defaults()
281 /* Command Register F, update -immediately- */ in init_reg_defaults()
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/OK3568_Linux_fs/kernel/arch/s390/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
65 u64 clock_comparator_max = -1ULL;
90 vdso_data->arch_data.tod_steering_end = tod_steering_end; in time_early_init()
108 * Scheduler clock - returns current time in nanosec units.
120 /* Split extendnd TOD clock to micro-seconds and sub-micro-seconds */ in ext_to_timespec64()
123 /* Calculate seconds and nano-seconds */ in ext_to_timespec64()
128 xt->tv_sec = sec; in ext_to_timespec64()
129 xt->tv_nsec = nsec; in ext_to_timespec64()
138 cd->event_handler(cd); in clock_comparator_work()
163 cd->name = "comparator"; in init_cpu_timer()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c1 // SPDX-License-Identifier: MIT
17 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on t…
18 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
26 * Indexes in h. code timing table for horizontal line position adjustment
34 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
173 { /* NTSC timing for 27 Mhz ref clk */
188 { /* PAL timing for 27 Mhz ref clk */
203 { /* NTSC timing for 14 Mhz ref clk */
218 { /* PAL timing for 14 Mhz ref clk */
240 struct drm_device *dev = radeon_encoder->base.dev; in radeon_legacy_tv_get_std_mode()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/dvm/
H A Drxon.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
14 #include "iwl-trans.h"
15 #include "iwl-modparams.h"
26 memset(&ctx->staging, 0, sizeof(ctx->staging)); in iwl_connection_init_rx_config()
28 if (!ctx->vif) { in iwl_connection_init_rx_config()
29 ctx->staging.dev_type = ctx->unused_devtype; in iwl_connection_init_rx_config()
31 switch (ctx->vif->type) { in iwl_connection_init_rx_config()
33 ctx->staging.dev_type = ctx->ap_devtype; in iwl_connection_init_rx_config()
[all …]
/OK3568_Linux_fs/kernel/Documentation/virt/kvm/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
13 2) Timing Devices
21 the virtualization of this platform is the plethora of timing devices available
32 information relevant to KVM and hardware-based virtualization.
34 2. Timing Devices
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
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