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12

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83867 ethernet PHY
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83867 device is a robust, low power, fully featured Physical Layer
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
[all …]
H A Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
24 and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA
[all …]
/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
18 #include <dt-bindings/net/ti-dp83867.h>
184 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
191 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
196 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
197 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
200 return -EINVAL; in dp83867_set_wol()
214 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
216 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dti.c2 * TI PHY drivers
4 * SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/net/ti-dp83867.h>
18 /* TI DP83867 */
83 /* User setting - can be taken from DTS */
102 * phy_read_mmd_indirect - reads data from the MMD registers
119 int value = -1; in phy_read_mmd_indirect()
136 * phy_write_mmd_indirect - writes data to the MMD registers
169 * dp83867_data_init - Convenience function for setting PHY specific data
175 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init() local
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/net/
H A Dti,dp83867.txt1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
17 ethernet-phy@0 {
19 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
20 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
21 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
25 http://www.ti.com/product/DP83867IR/datasheet
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
10 model = "TI DRA722 Rev C EVM";
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
[all …]
H A Ddra71-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
7 #include "dra7-mmc-iodelay.dtsi"
8 #include "dra72x-mmc-iodelay.dtsi"
9 #include <dt-bindings/net/ti-dp83867.h>
12 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
13 model = "TI DRA718 EVM";
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]
H A Ddra76-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-evm-common.dtsi"
9 #include "dra76x-mmc-iodelay.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 model = "TI DRA762 EVM";
14 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
28 reserved-memory {
29 #address-cells = <2>;
[all …]
H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 dsp_common_memory: dsp-common-memory@81f800000 {
[all …]
H A Drk3288-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec phyCORE-RK3288 SoM
8 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
29 ext_gmac: external-gmac-clock {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <125000000>;
33 clock-output-names = "ext_gmac";
36 leds: user-leds {
[all …]
H A Dimx7-mba7.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/net/ti-dp83867.h>
18 compatible = "gpio-beeper";
23 stdout-path = &uart6;
26 gpio_buttons: gpio-keys {
27 compatible = "gpio-keys";
29 button-0 {
36 button-1 {
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu102-revB.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2018, Xilinx, Inc.
10 #include "zynqmp-zcu102-revA.dts"
14 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
18 phy-handle = <&phyc>;
19 phyc: ethernet-phy@c {
21 ti,rx-internal-delay = <0x8>;
22 ti,tx-internal-delay = <0xa>;
23 ti,fifo-depth = <0x1>;
24 ti,dp83867-rxctrl-strap-quirk;
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP zc1751-xm016-dc2 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
85 phy-handle = <&phy0>;
[all …]
H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
51 phy-handle = <&phy0>;
52 phy-mode = "rgmii-id";
53 phy0: ethernet-phy@c {
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
42 gpio-keys {
43 compatible = "gpio-keys";
[all …]
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
42 gpio-keys {
43 compatible = "gpio-keys";
[all …]
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
42 gpio-keys {
43 compatible = "gpio-keys";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Ddra72-evm-revc.dts2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
8 #include "dra72-evm-common.dtsi"
9 #include <dt-bindings/net/ti-dp83867.h>
12 model = "TI DRA722 Rev C EVM";
28 #include "dra72-evm-tps65917.dtsi"
31 /* LDO2_OUT --> VDDA_1V8_PHY2 */
32 regulator-always-on;
33 regulator-boot-on;
37 vdda-supply = <&ldo2_reg>;
41 interrupt-parent = <&gpio3>;
[all …]
H A D.rk3288-phycore-rdk.dtb.d.pre.tmp
H A Ddra71-evm.dts2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
9 #include "dra72-evm-common.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
14 model = "TI DRA718 EVM";
21 vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
22 compatible = "regulator-gpio";
24 regulator-name = "vddshv8";
25 regulator-min-microvolt = <1800000>;
26 regulator-max-microvolt = <3000000>;
[all …]
H A D.rk3288-phycore-rdk.dtb.cmd
/OK3568_Linux_fs/u-boot/include/dt-bindings/net/
H A Dti-dp83867.h2 * TI DP83867 PHY drivers
4 * SPDX-License-Identifier: GPL-2.0
/OK3568_Linux_fs/kernel/include/dt-bindings/net/
H A Dti-dp83867.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Device Tree constants for the Texas Instruments DP83867 PHY
5 * Author: Dan Murphy <dmurphy@ti.com>
37 /* IO_MUX_CFG - Clock output selection */
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/net/ti-dp83867.h>
10 #include <dt-bindings/mux/ti-serdes.h>
14 stdout-path = "serial2:115200n8";
20 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
21 pinctrl-single,pins = <
37 mcu_mdio_pins_default: mcu-mdio1-pins-default {
[all …]
H A Dk3-am654-base-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-am654.dtsi"
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,am654-evm", "ti,am654";
17 stdout-path = "serial2:115200n8";
28 reserved-memory {
29 #address-cells = <2>;
[all …]

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