Searched +full:tegra30 +full:- +full:emc (Results 1 – 22 of 22) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra30 SoC External Memory Controller10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>15 The EMC interfaces with the off-chip SDRAM to service the request stream16 sent from Memory Controller. The EMC also has various performance-affecting[all …]
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra30 SoC Memory Controller10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>15 Tegra30 Memory Controller architecturally consists of the following parts:33 The Tegra30 Memory Controller handles memory requests from internal clients[all …]
1 # SPDX-License-Identifier: GPL-2.02 tegra-mc-y := mc.o4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o[all …]
1 # SPDX-License-Identifier: GPL-2.0-only15 This driver is for the External Memory Controller (EMC) found on16 Tegra20 chips. The EMC controls the external DRAM on the board.21 bool "NVIDIA Tegra30 External Memory Controller driver"25 This driver is for the External Memory Controller (EMC) found on26 Tegra30 chips. The EMC controls the external DRAM on the board.35 This driver is for the External Memory Controller (EMC) found on36 Tegra124 chips. The EMC controls the external DRAM on the board.49 This driver is for the External Memory Controller (EMC) found on50 Tegra210 chips. The EMC controls the external DRAM on the board.
1 // SPDX-License-Identifier: GPL-2.0+3 * Tegra30 External Memory Controller driver5 * Based on downstream driver from NVIDIA and tegra124-emc.c6 * Copyright (C) 2011-2014 NVIDIA Corporation9 * Copyright (C) 2019 GRATE-DRIVER project357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()377 struct tegra_emc *emc = data; in tegra_emc_isr() local[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */11 #include <asm/asm-offsets.h>143 * Puts the current CPU in wait-for-event mode on the flow controller144 * and powergates it -- flags (in R0) indicate the request type.147 * corrupts r0-r4, r10-r12152 cmp r10, #TEGRA30153 bne _no_cpu0_chk @ It's not Tegra30172 cmp r10, #TEGRA30197 cmp r10, #TEGRA30203 cmp r10, #TEGRA30[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-y += clk.o3 obj-y += clk-audio-sync.o4 obj-y += clk-dfll.o5 obj-y += clk-divider.o6 obj-y += clk-periph.o7 obj-y += clk-periph-fixed.o8 obj-y += clk-periph-gate.o9 obj-y += clk-pll.o10 obj-y += clk-pll-out.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <linux/clk-provider.h>16 #include <dt-bindings/clock/tegra30-car.h>19 #include "clk-id.h"583 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },593 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },594 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },595 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },599 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },600 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },[all …]
1 #include <dt-bindings/clock/tegra124-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra124-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/reset/tegra124-car.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>14 interrupt-parent = <&lic>;17 pcie-controller@01003000 {[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"12 memory-controller@7000f400 {13 emc-timings-0 {14 timing-667000000 {15 clock-frequency = <667000000>;17 nvidia,emc-auto-cal-interval = <0x001fffff>;18 nvidia,emc-mode-1 = <0x80100002>;19 nvidia,emc-mode-2 = <0x80200018>;20 nvidia,emc-mode-reset = <0x80000b71>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra124-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra124-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/reset/tegra124-car.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>9 #include <dt-bindings/soc/tegra-pmc.h>13 interrupt-parent = <&lic>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra30-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra30-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/soc/tegra-pmc.h>10 compatible = "nvidia,tegra30";11 interrupt-parent = <&lic>;12 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR MIT3 * Copyright 2016-2018 Toradex AG7 #include "tegra124-apalis-emc.dtsi"21 avddio-pex-supply = <®_1v05_vdd>;22 avdd-pex-pll-supply = <®_1v05_vdd>;23 avdd-pll-erefe-supply = <®_1v05_avdd>;24 dvddio-pex-supply = <®_1v05_vdd>;25 hvdd-pex-pll-e-supply = <®_module_3v3>;26 hvdd-pex-supply = <®_module_3v3>;27 vddio-pex-ctl-supply = <®_module_3v3>;[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR X113 * Copyright 2016-2019 Toradex AG7 #include "tegra124-apalis-emc.dtsi"20 avddio-pex-supply = <®_1v05_vdd>;21 avdd-pex-pll-supply = <®_1v05_vdd>;22 avdd-pll-erefe-supply = <®_1v05_avdd>;23 dvddio-pex-supply = <®_1v05_vdd>;24 hvdd-pex-pll-e-supply = <®_module_3v3>;25 hvdd-pex-supply = <®_module_3v3>;26 vddio-pex-ctl-supply = <®_module_3v3>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>7 #include "tegra124-jetson-tk1-emc.dtsi"11 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";17 /* This order keeps the mapping DB9 connector <-> ttyS0 */24 stdout-path = "serial0:115200n8";34 avddio-pex-supply = <&vdd_1v05_run>;35 dvddio-pex-supply = <&vdd_1v05_run>;36 avdd-pex-pll-supply = <&vdd_1v05_run>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra124-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra124-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>7 #include <dt-bindings/interrupt-controller/arm-gic.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>9 #include <dt-bindings/soc/tegra-pmc.h>13 interrupt-parent = <&lic>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include <dt-bindings/power/tegra194-powergate.h>8 #include <dt-bindings/reset/tegra194-reset.h>9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>10 #include <dt-bindings/memory/tegra194-mc.h>[all …]
2 # (C) Copyright 2010-2015 Nvidia Corporation.4 # (C) Copyright 2000-20087 # SPDX-License-Identifier: GPL-2.0+12 obj-y += spl.o13 obj-y += cpu.o15 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o18 obj-y += ap.o19 obj-y += board.o board2.o20 obj-y += cache.o21 obj-y += clock.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only60 * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is81 * struct tegra_devfreq_device_config - configuration specific to an ACTMON101 * increasing the EMC frequency when the CPU is very busy but not135 * struct tegra_devfreq_device - state specific to an ACTMON device195 return readl_relaxed(tegra->regs + offset); in actmon_readl()200 writel_relaxed(val, tegra->regs + offset); in actmon_writel()205 return readl_relaxed(dev->regs + offset); in device_readl()211 writel_relaxed(val, dev->regs + offset); in device_writel()229 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()[all …]
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