Searched +full:tegra124 +full:- +full:mc (Results 1 – 19 of 19) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra124 SoC Memory Controller10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.16 two memory channels. The Tegra124 Memory Controller handles memory requests22 const: nvidia,tegra124-mc[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra124 SoC External Memory Controller10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 The EMC interfaces with the off-chip SDRAM to service the request stream19 const: nvidia,tegra124-emc26 - description: external memory clock[all …]
1 # SPDX-License-Identifier: GPL-2.02 tegra-mc-y := mc.o4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o[all …]
1 # SPDX-License-Identifier: GPL-2.0-only7 This driver supports the Memory Controller (MC) hardware found on31 bool "NVIDIA Tegra124 External Memory Controller driver"36 Tegra124 chips. The EMC controls the external DRAM on the board.
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <linux/dma-mapping.h>20 #include "mc.h"24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },45 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Based on downstream driver from NVIDIA and tegra124-emc.c6 * Copyright (C) 2011-2014 NVIDIA Corporation9 * Copyright (C) 2019 GRATE-DRIVER project29 #include "mc.h"328 struct tegra_mc *mc; member362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <linux/clk-provider.h>23 #include <soc/tegra/mc.h>466 struct tegra_mc *mc; member491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <dt-bindings/memory/tegra124-mc.h>11 #include "mc.h"721 /* read-only */736 /* read-only */
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra124-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra124-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/reset/tegra124-car.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>9 #include <dt-bindings/soc/tegra-pmc.h>12 compatible = "nvidia,tegra124";[all …]
1 #include <dt-bindings/clock/tegra124-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra124-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/reset/tegra124-car.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>13 compatible = "nvidia,tegra124";14 interrupt-parent = <&lic>;[all …]
1 #include <dt-bindings/clock/tegra210-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra210-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>10 interrupt-parent = <&lic>;11 #address-cells = <2>;12 #size-cells = <2>;14 pcie-controller@01003000 {[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra124-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra124-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>7 #include <dt-bindings/interrupt-controller/arm-gic.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>9 #include <dt-bindings/soc/tegra-pmc.h>12 compatible = "nvidia,tegra132", "nvidia,tegra124";[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
4 - compatible : Must contain one of the following values:5 - "nvidia,tegra20-vde"6 - "nvidia,tegra30-vde"7 - "nvidia,tegra114-vde"8 - "nvidia,tegra124-vde"9 - "nvidia,tegra132-vde"10 - reg : Must contain an entry for each entry in reg-names.11 - reg-names : Must include the following entries:12 - sxe13 - bsev[all …]
2 * (C) Copyright 2010-20155 * SPDX-License-Identifier: GPL-2.0+14 #include <asm/arch/mc.h>15 #include <asm/arch-tegra/ap.h>16 #include <asm/arch-tegra/clock.h>17 #include <asm/arch-tegra/fuse.h>18 #include <asm/arch-tegra/pmc.h>19 #include <asm/arch-tegra/scu.h>20 #include <asm/arch-tegra/tegra.h>21 #include <asm/arch-tegra/warmboot.h>[all …]
2 * (C) Copyright 2010-20155 * SPDX-License-Identifier: GPL-2.0+15 #include <asm/arch/mc.h>17 #include <asm/arch-tegra/ap.h>18 #include <asm/arch-tegra/board.h>19 #include <asm/arch-tegra/pmc.h>20 #include <asm/arch-tegra/sys_proto.h>21 #include <asm/arch-tegra/warmboot.h>54 #error tegra_cpu_is_non_secure has only been validated on Tegra12459 * This register reads 0xffffffff in non-secure mode. This register in tegra_cpu_is_non_secure()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.7 #include <linux/clk-provider.h>14 #include <dt-bindings/clock/tegra124-car.h>15 #include <dt-bindings/reset/tegra124-car.h>18 #include "clk-id.h"22 * banks present in the Tegra124/132 CAR IP block. The banks are95 #define MASK(x) (BIT(x) - 1)995 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.34 #include <dt-bindings/thermal/tegra124-soctherm.h>197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...