Searched +full:sun9i +full:- +full:a80 +full:- +full:mmc +full:- +full:clk (Results 1 – 9 of 9) sorted by relevance
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms47 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/pinctrl/sun4i-a10.h>52 interrupt-parent = <&gic>;55 #address-cells = <1>;56 #size-cells = <0>;59 compatible = "arm,cortex-a7";65 compatible = "arm,cortex-a7";[all …]
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun9i-a80-ccu.h>48 #include <dt-bindings/clock/sun9i-a80-de.h>49 #include <dt-bindings/clock/sun9i-a80-usb.h>50 #include <dt-bindings/reset/sun9i-a80-ccu.h>51 #include <dt-bindings/reset/sun9i-a80-de.h>52 #include <dt-bindings/reset/sun9i-a80-usb.h>[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A80 MMC Configuration Clock Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>16 There is one clock/reset output per mmc controller. The number of18 related to the overall mmc block.21 "#clock-cells":[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>16 "#clock-cells":25 - allwinner,sun4i-a10-mmc-clk26 - allwinner,sun9i-a80-mmc-clk37 clock-output-names:[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Copyright 2015 Chen-Yu Tsai5 * Chen-Yu Tsai <wens@csie.org>8 #include <linux/clk.h>9 #include <linux/clk-provider.h>17 #include <linux/reset-controller.h>29 struct clk *clk; member42 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; in sun9i_mmc_reset_assert()45 clk_prepare_enable(data->clk); in sun9i_mmc_reset_assert()46 spin_lock_irqsave(&data->lock, flags); in sun9i_mmc_reset_assert()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later8 #include <linux/clk.h>9 #include <linux/clk-provider.h>15 #include "clk-factors.h"18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Driver for sunxi SD/MMC host controllers4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>12 #include <linux/clk.h>13 #include <linux/clk/sunxi-ng.h>16 #include <linux/dma-mapping.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.6 #include <linux/clk-provider.h>21 #include "ccu-sun9i-a80.h"28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",95 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",111 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",[all …]
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