Searched +full:sun5i +full:- +full:a13 +full:- +full:mbus +full:- +full:clk (Results 1 – 10 of 10) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A10 MBUS Clock Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>16 "#clock-cells":21 - allwinner,sun5i-a13-mbus-clk22 - allwinner,sun8i-a23-mbus-clk[all …]
2 * Copyright 2012-2015 Maxime Ripard4 * Maxime Ripard <maxime.ripard@free-electrons.com>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/clock/sun5i-ccu.h>46 #include <dt-bindings/dma/sun4i-a10.h>47 #include <dt-bindings/reset/sun5i-ccu.h>50 interrupt-parent = <&intc>;51 #address-cells = <1>;52 #size-cells = <1>;55 #address-cells = <1>;[all …]
2 * Copyright 2012-2015 Maxime Ripard4 * Maxime Ripard <maxime.ripard@free-electrons.com>6 * This file is dual-licensed: you can use it either under the terms47 #include <dt-bindings/clock/sun4i-a10-pll2.h>48 #include <dt-bindings/dma/sun4i-a10.h>49 #include <dt-bindings/pinctrl/sun4i-a10.h>52 interrupt-parent = <&intc>;55 #address-cells = <1>;56 #size-cells = <0>;60 compatible = "arm,cortex-a8";[all …]
4 * Mylène Josserand <mylene.josserand@free-electrons.com>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/clock/sun4i-a10-pll2.h>46 #include <dt-bindings/dma/sun4i-a10.h>47 #include <dt-bindings/pinctrl/sun4i-a10.h>50 interrupt-parent = <&intc>;51 #address-cells = <1>;52 #size-cells = <1>;55 #address-cells = <1>;56 #size-cells = <0>;[all …]
4 * Maxime Ripard <maxime.ripard@free-electrons.com>6 * This file is dual-licensed: you can use it either under the terms47 #include <dt-bindings/interrupt-controller/arm-gic.h>48 #include <dt-bindings/thermal/thermal.h>50 #include <dt-bindings/clock/sun4i-a10-pll2.h>51 #include <dt-bindings/dma/sun4i-a10.h>52 #include <dt-bindings/pinctrl/sun4i-a10.h>55 interrupt-parent = <&gic>;62 #address-cells = <1>;63 #size-cells = <1>;[all …]
6 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c7 * and earlier U-Boot Allwiner A10 SPL work9 * (C) Copyright 2007-201214 * SPDX-License-Identifier: GPL-2.0+69 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()70 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()74 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()82 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later8 #include <linux/clk.h>9 #include <linux/clk-provider.h>15 #include "clk-factors.h"18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/sun50i-a64-ccu.h>7 #include <dt-bindings/clock/sun8i-de2.h>8 #include <dt-bindings/clock/sun8i-r-ccu.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/reset/sun50i-a64-ccu.h>11 #include <dt-bindings/reset/sun8i-de2.h>12 #include <dt-bindings/reset/sun8i-r-ccu.h>13 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 #include <linux/clk-provider.h>24 #include "ccu-sun5i.h"34 .hw.init = CLK_HW_INIT("pll-core",46 * With sigma-delta modulation for fractional-N on the audio PLL,74 .hw.init = CLK_HW_INIT("pll-audio-base",91 .hw.init = CLK_HW_INIT("pll-video0",106 .hw.init = CLK_HW_INIT("pll-ve",119 .hw.init = CLK_HW_INIT("pll-ddr-base",126 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,[all …]
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