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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.mpc85xx-spin-table1 Spin table in cache
3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
6 __secondary_start_page. For other cores to use the spin table, the booting
15 core 0 puts the physical address of the spin table (which is in release.S and
21 the new space. The new TLB covers the physical address of the spin table page,
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
23 without stress DDR bus because both the code and the spin table is in cache.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-spin-table.dtsi4 * ARMv8 Foundation model DTS (spin table configuration)
8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
H A Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dselftest_mocs.c2 * SPDX-License-Identifier: MIT
30 ce->ring = __intel_context_ring_size(SZ_16K); in mocs_context_create()
40 err = -ETIME; in request_add_sync()
46 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument
52 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin()
53 err = -ETIME; in request_add_spin()
65 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
71 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL); in create_scratch()
88 struct drm_i915_mocs_table table; in live_mocs_init() local
94 flags = get_mocs_settings(gt->i915, &table); in live_mocs_init()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
95 /* Enable/invalidate the I-Cache */
113 /* Enable/invalidate the D-Cache */
131 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
133 /* get our PIR to figure out our table entry */
142 * 0-17 Reserved (logic 0s)
143 * 18-19 CHIP_ID, 2'b00 - SoC 1
144 * all others - reserved
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dbcm2837.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
27 always-on;
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/
H A DKconfig4 bool "Enable multiple CPUs to enter into U-Boot"
10 CPUECTLR_EL1.SMPEN bit before U-Boot.
25 bool "Support spin-table enable method"
28 Say Y here to support "spin-table" enable method for booting Linux.
31 - Specify enable-method = "spin-table" in each CPU node in the
33 - Bring secondary CPUs into U-Boot proper in a board specific
35 secondary CPUs will spin in unprotected memory area because the
36 master CPU protects the relocated spin code.
38 U-Boot automatically does:
39 - Set "cpu-release-addr" property of each CPU node
[all …]
H A Dspin_table.c5 * SPDX-License-Identifier: GPL-2.0+
18 unsigned long rsv_size = &spin_table_reserve_end - in spin_table_update_dt()
23 return -ENODEV; in spin_table_update_dt()
34 * spin-table. Otherwise, just return successfully to not in spin_table_update_dt()
37 prop = fdt_getprop(fdt, offset, "enable-method", NULL); in spin_table_update_dt()
38 if (!prop || strcmp(prop, "spin-table")) in spin_table_update_dt()
49 ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr", in spin_table_update_dt()
52 return -ENOSPC; in spin_table_update_dt()
57 return -ENOSPC; in spin_table_update_dt()
59 printf(" Reserved memory region for spin-table: addr=%lx size=%lx\n", in spin_table_update_dt()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/toshiba/
H A Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
[all …]
/OK3568_Linux_fs/yocto/poky/bitbake/lib/toaster/toastergui/static/css/
H A Ddefault.css4 body { padding-top: 50px; }
7 img.logo { height: 30px; vertical-align: bottom; }
10 .toaster-navbar-brand { float: left; margin: 7px 25px 0 0; }
11 .toaster-navbar-brand a.brand { color: #777; height: 50px; padding: 15px 5px 15px 15px; font-size: …
12 .toaster-navbar-brand > a { text-decoration: none; }
13 .toaster-navbar-brand > a.brand:hover { color: #5e5e5e; }
16 .glyphicon-info-sign { color: #777; font-size: 16px; }
17 .glyphicon-info-sign:hover { color: #999; cursor: pointer; }
19 /* Override the negative right margin for the navbar-right class */
20 #new-project-button { margin-right: 0; }
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/85xx/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
26 #include <asm/code-patching.h>
58 qoriq_pm_ops->freeze_time_base(true); in mpc85xx_give_timebase()
61 * e5500/e6500 have a workaround for erratum A-006958 in place in mpc85xx_give_timebase()
62 * that will reread the timebase until TBL is non-zero. in mpc85xx_give_timebase()
66 * TBL is non-zero, we ensure that TB does not change. We don't in mpc85xx_give_timebase()
91 qoriq_pm_ops->freeze_time_base(false); in mpc85xx_give_timebase()
122 qoriq_pm_ops->irq_mask(cpu); in smp_85xx_cpu_offline_self()
131 cur_cpu_spec->cpu_down_flush(); in smp_85xx_cpu_offline_self()
[all …]
/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dmp.h2 * Copyright 2014-2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 * Each spin table element is defined as
19 * the actual spin table is an array of these structures
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/
H A Dlowlevel_init_gen3.S12 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm-offsets.h>
25 * For single-entry systems the lowlevel init is very simple.
50 * Slave should wait for master clearing spin table.
52 * value of spin table and jumping to wrong place.
/OK3568_Linux_fs/kernel/kernel/locking/
H A Dqspinlock_paravirt.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
17 * pv_kick(cpu) -- wakes a suspended vcpu
31 * mitigates the slight slowdown for non-overcommitted guest with this
32 * aggressive wait-early mechanism.
64 * pv_wait_head_or_lock() to signal that it is ready to spin on the lock.
88 int val = atomic_read(&lock->val); in pv_hybrid_queued_unfair_trylock()
91 (cmpxchg_acquire(&lock->locked, 0, _Q_LOCKED_VAL) == 0)) { in pv_hybrid_queued_unfair_trylock()
111 WRITE_ONCE(lock->pending, 1); in set_pending()
121 return !READ_ONCE(lock->locked) && in trylock_clear_pending()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S2 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch-fsl-layerscape/soc.h>
18 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
20 #include <asm/u-boot.h>
80 /* Set Wuo bit for RN-I 20 */
87 * Set forced-order mode in RNI-6, RNI-20
89 * LS2080A family does not support setting forced-order mode,
107 /* Add fully-coherent masters to DVM domain */
113 /* Set all RN-I ports to QoS of 15 */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/kernel/
H A Dsmp_spin_table.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Spin Table SMP initialisation
50 return -ENODEV; in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
71 return -ENODEV; in smp_spin_table_cpu_prepare()
74 * The cpu-release-addr may or may not be inside the linear mapping. in smp_spin_table_cpu_prepare()
82 return -ENOMEM; in smp_spin_table_cpu_prepare()
86 * endianness of the kernel. Therefore, any boot-loaders that in smp_spin_table_cpu_prepare()
88 * boot-loader's endianness before jumping. This is mandated by in smp_spin_table_cpu_prepare()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/44x/
H A Diss4xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
12 * Copyright (c) 2003-2005 Zultys Technologies
54 for_each_node_with_property(np, "interrupt-controller") { in iss4xx_init_irq()
66 } else if (of_device_is_compatible(np, "chrp,open-pic")) { in iss4xx_init_irq()
68 * device-tree, just pass 0 to all arguments in iss4xx_init_irq()
94 /* Assume spin table. We could test for the enable-method in in smp_iss4xx_kick_cpu()
95 * the device-tree but currently there's little point as it's in smp_iss4xx_kick_cpu()
98 spin_table_addr_prop = of_get_property(cpunode, "cpu-release-addr", in smp_iss4xx_kick_cpu()
101 pr_err("CPU%d: Can't start, missing cpu-release-addr !\n", cpu); in smp_iss4xx_kick_cpu()
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Drhashtable-types.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Resizable, Scalable, Concurrent Hash Table
29 * struct rhashtable_compare_arg - Key for the function rhashtable_compare
30 * @ht: Hash table
44 * struct rhashtable_params - Hash table construction parameters
70 * struct rhashtable - Hash table handle
71 * @tbl: Bucket table
73 * @max_elems: Maximum number of elements in table
77 * @mutex: Mutex to protect current/future table swapping
78 * @lock: Spin lock to protect walker list
[all …]

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