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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dhisilicon,hi6220-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi6220 SoC.
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
21 compatible = "hisilicon,hi6220-sysctrl", "syscon";
23 #clock-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk1808.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/clock/rk1808-cru.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/power/rk1808-power.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/soc/rockchip-system-status.h>
12 #include <dt-bindings/suspend/rockchip-rk1808.h>
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3399.h>
[all …]
H A Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/display/media-bus-format.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/suspend/rockchip-rk3308.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dinno_rk3036.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Zheng ShunQian<zhengsq@rock-chips.com>
9 #include <sound/soc.h>
11 #include <sound/soc-dapm.h>
12 #include <sound/soc-dai.h>
22 #include <linux/mfd/syscon.h>
36 static const DECLARE_TLV_DB_MINMAX(rk3036_codec_hp_tlv, -39, 0);
41 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rk3036_codec_antipop_event()
44 regmsk = INNO_R09_HP_ANTIPOP_MSK << w->shift; in rk3036_codec_antipop_event()
47 val = INNO_R09_HP_ANTIPOP_ON << w->shift; in rk3036_codec_antipop_event()
[all …]
H A Dmsm8916-wcd-digital.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/mfd/syscon.h>
14 #include <sound/soc.h>
331 /* Digital Gain control -84 dB to +40 dB in 1 dB steps */
332 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
334 /* Cutoff Freq for High Pass Filter at -3dB */
360 snd_soc_dapm_to_component(w->dapm); in msm8x16_wcd_codec_set_iir_gain()
365 if (w->shift == 0) in msm8x16_wcd_codec_set_iir_gain()
367 else if (w->shift == 1) in msm8x16_wcd_codec_set_iir_gain()
428 struct wcd_iir_filter_ctl *ctl = in msm8x16_wcd_get_iir_band_audio_mixer() local
[all …]
H A Drk312x_codec.c29 #include <linux/mfd/syscon.h>
36 #include <sound/soc.h>
37 #include <sound/soc-dapm.h>
42 #include <linux/extcon-provider.h>
45 static int debug = -1;
56 #define INVALID_GPIO -1
63 * 0: -39dB
71 * 0: -18db
76 #define CAP_VOL 26 /*0-31 */
258 return -EINVAL; in rk312x_codec_ctl_gpio()
[all …]
H A Drv1106_codec.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rv1106_codec.c - Rockchip RV1106 SoC Codec Driver
11 #include <linux/mfd/syscon.h>
21 #include <sound/soc.h>
32 #define CODEC_DRV_NAME "rv1106-acodec"
53 #define NOT_SPECIFIED (-1)
62 SING_ADCL, /* Single-end ADCL, the ADCR is not used */
64 SING_ADCR, /* Single-end ADCR, the ADCL is not used */
65 SING_ADCLR, /* Single-end ADCL and ADCR */
119 -1800, 150, 2850);
[all …]
H A Drk3308_codec.c2 * rk3308_codec.c -- RK3308 ALSA Soc Audio Driver
25 #include <linux/mfd/syscon.h>
43 #include <sound/soc.h>
54 #define CODEC_DRV_NAME "rk3308-acodec"
167 * grp 0 -- select ADC1 / ADC2
168 * grp 1 -- select ADC3 / ADC4
169 * grp 2 -- select ADC5 / ADC6
170 * grp 3 -- select ADC7 / ADC8
204 /* Only hpout do fade-in and fade-out */
228 -1800, 150, 2850);
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/power/rk3036-power.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/qcom/
H A Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
24 #include <linux/mfd/syscon.h>
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
125 #define FUSE_REVISION_UNKNOWN (-1)
254 return !drv->loop_disabled; in cpr_is_allowed()
259 writel_relaxed(value, drv->base + offset); in cpr_write()
264 return readl_relaxed(drv->base + offset); in cpr_read()
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3399.dtsi2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3399-power.h>
13 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
[all …]
H A D.OK3568-C.dtb.dts.tmp
H A D.rk3399-evb.dtb.dts.tmp
H A D.rk3399-firefly.dtb.dts.tmp
H A D.rk3399-puma-ddr1600.dtb.dts.tmp
H A D.rk3399-puma-ddr1866.dtb.dts.tmp
H A D.rk3399-puma-ddr1333.dtb.dts.tmp

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