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/optee_os/core/arch/riscv/plat-sifive/
H A Dplatform_config.h3 * Copyright (c) 2025 SiFive, Inc
12 /* SiFive UART */
H A Dmain.c3 * Copyright (c) 2025 SiFive, Inc
/optee_os/core/drivers/
H A Dsifive_uart.c3 * Copyright (c) 2025 SiFive, Inc
9 /* SiFive UART register defines */
18 /* SiFive UART status register bits */
/optee_os/core/arch/riscv/include/kernel/
H A Driscv_elf.h3 * Copyright (c) 2025 SiFive, Inc
/optee_os/core/include/drivers/
H A Dsifive_uart.h3 * Copyright (c) 2025 SiFive, Inc
/optee_os/.github/workflows/
H A Dci.yml339 _make PLATFORM=sifive