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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 reg = <0x0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 reg = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-bcm/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
106 return -EINVAL; in nsp_write_lut()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <linux/irqchip/arm-gic-v3.h>
71 * so we need some other way of telling a new secondary core
101 return -ENOSYS; in op_cpu_kill()
107 * Boot a secondary CPU, and assign it the specified idle task.
114 if (ops->cpu_boot) in boot_secondary()
115 return ops->cpu_boot(cpu); in boot_secondary()
117 return -EOPNOTSUPP; in boot_secondary()
128 * We need to tell the secondary core where to find its stack and the in __cpu_up()
139 pr_err("CPU%u: failed to boot: %d\n", cpu, ret); in __cpu_up()
[all …]
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
18 * snapshot state to indicate the lowest-common denominator of the feature,
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm23550.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
37 #include "dt-bindings/clock/bcm21664.h"
40 #address-cells = <1>;
41 #size-cells = <1>;
44 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a7";
53 reg = <0>;
[all …]
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
[all …]
H A Dhip01-ca9x2.dts1 // SPDX-License-Identifier: GPL-2.0-only
11 /dts-v1/;
13 /* First 8KB reserved for secondary core boot */
20 compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
23 #address-cells = <1>;
24 #size-cells = <0>;
25 enable-method = "hisilicon,hip01-smp";
29 compatible = "arm,cortex-a9";
30 reg = <0>;
35 compatible = "arm,cortex-a9";
[all …]
H A Darm-realview-eb-mp.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
42 reg:
54 Bits [11:0] in the reg cell must be set to
57 All other bits in the reg cell must be set to 0.
[all …]
H A Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
19 ---------------------------------------------------------------
34 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
36 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
42 model = "Sony NSZ-GS7";
43 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
54 - compatible: should be "marvell,berlin-cpu-ctrl"
55 - reg: address and length of the register set
59 cpu-ctrl@f7dd0000 {
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/openrisc/opencores/
H A Dor1ksim.txt6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
21 #include <asm/processor-flags.h>
26 #include <asm/nospec-branch.h>
30 #include <asm/asm-offsets.h>
32 #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg argument
35 #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg argument
40 * because we need identity-mapped pages.
43 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
64 * arch/x86/boot/compressed/head_64.S.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/img/
H A Dpistachio.txt5 --------------------
6 - compatible: Must include "img,pistachio".
9 ----------
11 - #address-cells: Must be 1.
12 - #size-cells: Must be 0.
13 A CPU sub-node is also required for at least CPU 0. Since the topology may
14 be probed via CPS, it is not necessary to specify secondary CPUs. Required
16 - device_type: Must be "cpu".
17 - compatible: Must be "mti,interaptiv".
18 - reg: CPU number.
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S2 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch-fsl-layerscape/soc.h>
18 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
20 #include <asm/u-boot.h>
61 /* Kick secondary cpus up by SGI 0 interrupt */
80 /* Set Wuo bit for RN-I 20 */
87 * Set forced-order mode in RNI-6, RNI-20
89 * LS2080A family does not support setting forced-order mode,
107 /* Add fully-coherent masters to DVM domain */
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/typec/ucsi/
H A Ducsi_ccg.c1 // SPDX-License-Identifier: GPL-2.0
3 * UCSI driver for Cypress CCGx Type-C controller
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
25 BOOT, /* bootloader */ enumerator
26 FW1, /* FW partition-1 (contains secondary fw) */
27 FW2, /* FW partition-2 (contains primary fw) */
85 SECONDARY_BL, /* update secondary using bootloader */
86 PRIMARY, /* update primary using secondary */
87 SECONDARY, /* update secondary using primary */ enumerator
170 u16 reg; member
[all …]
/OK3568_Linux_fs/kernel/drivers/iio/imu/st_lsm6dsx/
H A Dst_lsm6dsx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 #define ST_LSM6DS3TRC_DEV_NAME "lsm6ds3tr-c"
28 #define ST_LSM9DS1_DEV_NAME "lsm9ds1-imu"
116 struct st_lsm6dsx_reg reg; member
129 struct st_lsm6dsx_reg reg; member
136 * struct st_lsm6dsx_fifo_ops - ST IMU FIFO settings
158 * struct st_lsm6dsx_hw_ts_settings - ST IMU hw timer settings
174 * struct st_lsm6dsx_shub_settings - ST IMU hw i2c controller settings
177 * @pullup_en: i2c controller pull-up register info (addr + mask).
183 * @slv0_addr: slave0 address in secondary page.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-qcom/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
58 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); in scss_release_secondary()
61 return -ENXIO; in scss_release_secondary()
67 return -ENOMEM; in scss_release_secondary()
81 void __iomem *reg, *saw_reg; in kpssv1_release_secondary() local
87 return -ENODEV; in kpssv1_release_secondary()
91 ret = -ENODEV; in kpssv1_release_secondary()
97 ret = -ENODEV; in kpssv1_release_secondary()
101 reg = of_iomap(acc_node, 0); in kpssv1_release_secondary()
102 if (!reg) { in kpssv1_release_secondary()
[all …]
/OK3568_Linux_fs/kernel/arch/sparc/kernel/
H A Dsbus.c1 // SPDX-License-Identifier: GPL-2.0
36 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
37 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
38 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
39 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
40 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
41 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
42 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
43 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
49 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dcpu.c4 * SPDX-License-Identifier: GPL-2.0+
121 * The base address of TTLB is gd->arch.tlb_addr. We use two
122 * levels of translation tables here to cover 40-bit address space.
128 * ------- <---- 0GB
131 * |-------| <---- 0x24000000
133 * |-------| <---- 0x300000000
135 * |-------| <---- 0x34000000
137 * |-------| <---- 0x40000000
139 * |-------| <---- 0x80000000 DDR0 space start
143 * ------- <---- 4GB DDR0 space end
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/kernel/
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
23 #include <asm/reg.h>
27 #include <asm/head-64.h>
28 #include <asm/asm-offsets.h>
41 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
[all …]

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