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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dbrcm,sdhci-iproc.txt1 Broadcom IPROC SDHCI controller
4 by mmc.txt and the properties that represent the IPROC SDHCI controller.
7 - compatible : Should be one of the following
8 "brcm,bcm2835-sdhci"
9 "brcm,bcm2711-emmc2"
10 "brcm,sdhci-iproc-cygnus"
11 "brcm,sdhci-iproc"
13 Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
14 bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
16 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
[all …]
H A Dmarvell,xenon-sdhci.txt1 Marvell Xenon SDHCI Controller device tree bindings
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
22 - clock-names:
27 - reg:
28 * For "marvell,armada-3700-sdhci", two register areas.
[all …]
H A Dnvidia,tegra20-sdhci.txt7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
18 - clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
[all …]
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
[all …]
H A Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
[all …]
H A Daspeed,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
16 Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
[all …]
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Device Tree Bindings for the Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
[all …]
H A Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA SDHCI v2/v3 bindings
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
[all …]
H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - ti,am654-sdhci-5.1
20 - ti,j721e-sdhci-8bit
21 - ti,j721e-sdhci-4bit
[all …]
H A Dsdhci-of-dwcmshc.txt4 - compatible: should be one of the following:
5 "snps,dwcmshc-sdhci"
6 - reg: offset and length of the register set for the device.
7 - interrupts: a single interrupt specifier.
8 - clocks: Array of clocks required for SDHCI; requires at least one for
10 - clock-names: Array of names corresponding to clocks property; shall be
14 sdhci2: sdhci@aa0000 {
15 compatible = "snps,dwcmshc-sdhci";
19 bus-width = <8>;
H A Dmicrochip,dw-sparx5-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml"
13 - Lars Povlsen <lars.povlsen@microchip.com>
18 const: microchip,dw-sparx5-sdhci
29 Handle to "core" clock for the sdhci controller.
31 clock-names:
33 - const: core
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
21 17 sdio SDHCI Host
29 -----------------------------------
35 8 audio Audio Cntrl
40 17 sdio SDHCI Host
56 -----------------------------------
64 8 pex0 PCIe 0
83 -----------------------------------
87 8 pex0 PCIe 0
97 -----------------------------------
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
9 * SDHCI (HSMMC) support for Samsung SoC
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
29 #include "sdhci.h"
63 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
86 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
[all …]
H A Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for SDHCI on STMicroelectronics SoCs
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
31 #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
59 #define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
72 #define ST_MMC_CCONFIG_DDR50 BIT(8)
78 #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
97 #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
[all …]
H A Dsdhci-pltfm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-pltfm.c Support for SDHCI platform devices
14 * SDHCI platform devices
16 * Inspired by sdhci-pci.c, by Pierre Ossman
26 #include "sdhci-pltfm.h"
32 return clk_get_rate(pltfm_host->clk); in sdhci_pltfm_clk_get_max_clock()
45 if (device_property_present(dev, "sdhci,wp-inverted") || in sdhci_wp_inverted()
46 device_property_present(dev, "wp-inverted")) in sdhci_wp_inverted()
49 /* Old device trees don't have the wp-inverted property. */ in sdhci_wp_inverted()
61 struct device_node *np = pdev->dev.of_node; in sdhci_get_compatibility()
[all …]
H A Dsdhci-of-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
37 struct aspeed_sdhci *sdhci, in aspeed_sdc_configure_8bit_mode() argument
42 /* Set/clear 8 bit mode */ in aspeed_sdc_configure_8bit_mode()
43 spin_lock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
44 info = readl(sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
46 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
48 info &= ~sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
49 writel(info, sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
50 spin_unlock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
[all …]
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dbcm2835_sdhci.c3 * git://github.com/gonzoua/u-boot-pi.git master
6 * Tweaks for U-Boot upstreaming
9 * Portions (e.g. read/write macros, concepts for back-to-back register write
11 * https://github.com/raspberrypi/linux.git rpi-3.6.y
16 * Support for SDHCI device on 2835
17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom
34 * SDHCI platform device - Arasan SD controller in BCM2708
36 * Inspired by sdhci-pci.c, by Pierre Ossman
43 #include <sdhci.h>
46 #include <mach/sdhci.h>
[all …]
H A DKconfig25 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
26 and non-removable (e.g. eMMC chip) devices are supported. These
27 appear as block devices in U-Boot and can support filesystems such
36 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
37 and non-removable (e.g. eMMC chip) devices are supported. These
38 appear as block devices in U-Boot and can support filesystems such
49 you are reading this help text, you most likely have no idea :-)
113 as removeable SD and micro-SD cards.
155 This selects PCI-based MMC controllers.
174 This enables extended-drain in the MMC/SD/SDIO1I/O and
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra30-tamonten.dtsi5 compatible = "ad,tamonten-ng", "nvidia,tegra30";
12 stdout-path = &uartd;
21 mmc0 = "/sdhci@78000600";
22 mmc1 = "/sdhci@78000400";
23 mmc2 = "/sdhci@78000000";
30 clock-frequency = <100000>;
35 clock-frequency = <100000>;
41 clock-frequency = <100000>;
47 clock-frequency = <100000>;
53 clock-frequency = <100000>;
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
18 mmc0 = "/sdhci@78000600";
19 mmc1 = "/sdhci@78000400";
20 mmc2 = "/sdhci@78000000";
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra210-p2371-0000.dts1 /dts-v1/;
6 model = "NVIDIA P2371-0000";
7 compatible = "nvidia,p2371-0000", "nvidia,tegra210";
10 stdout-path = &uarta;
15 mmc0 = "/sdhci@700b0600";
16 mmc1 = "/sdhci@700b0000";
24 sdhci@700b0000 {
26 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
27 power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
28 bus-width = <4>;
[all …]
H A Dtegra210-e2220-1170.dts1 /dts-v1/;
6 model = "NVIDIA E2220-1170";
7 compatible = "nvidia,e2220-1170", "nvidia,tegra210";
10 stdout-path = &uarta;
15 mmc0 = "/sdhci@700b0600";
16 mmc1 = "/sdhci@700b0000";
24 sdhci@700b0000 {
26 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
27 power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
28 bus-width = <4>;
[all …]
H A Dtegra186-p2771-0000.dtsi4 model = "NVIDIA P2771-0000";
5 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
8 stdout-path = &uarta;
12 mmc0 = "/sdhci@3460000";
13 mmc1 = "/sdhci@3400000";
30 phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
49 sdhci@3400000 {
51 wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
52 bus-width = <4>;
55 sdhci@3460000 {
[all …]

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