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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml90 cdns,phy-dll-delay-sdclk:
92 Value of the delay introduced on the sdclk output for all modes except
98 cdns,phy-dll-delay-sdclk-hsmmc:
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
133 cdns,phy-dll-delay-sdclk = <0>;
H A Dmarvell,xenon-sdhci.txt131 clocks = <&sdclk>, <&axi_clk>;
167 clocks = <&sdclk>;
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Duniphier-sd.c65 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
66 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
67 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
68 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
69 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
70 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
71 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
72 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
74 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
[all …]
H A Dsdhci-cadence.c63 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
64 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
H A Ds5p_sdhci.c55 * Inverter delay means10ns delay if SDCLK 50MHz setting in s5p_sdhci_set_control_reg()
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-xenon-phy.c222 * 1. SDCLK frequency changes.
223 * 2. SDCLK is stopped and re-enabled.
460 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
482 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
771 * PHY setting should be adjusted when SDCLK frequency, Bus Width
H A Dsdhci-cadence.c88 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
89 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
H A Dsdhci-xenon.c50 /* Set SDCLK-off-while-idle */
460 /* Disable SDCLK-Off-While-Idle before card init */ in xenon_sdhc_prepare()
H A Dsdhci-of-aspeed.c269 dev_err(&pdev->dev, "Unable to enable SDCLK\n"); in aspeed_sdc_probe()
/OK3568_Linux_fs/u-boot/drivers/ram/
H A Dstm32_sdram.c112 u8 sdclk; member
176 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT in stm32_sdram_init()
/OK3568_Linux_fs/u-boot/board/imx31_phycore/
H A Dlowlevel_init.S47 REG 0x43FAC26C, 0 /* SDCLK */
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dsa1110-cpufreq.c152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
153 * run SDCLK at half speed. in sdram_calculate_timing()
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Duniphier-ld11.dtsi284 cdns,phy-dll-delay-sdclk = <21>;
285 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi358 cdns,phy-dll-delay-sdclk = <21>;
359 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-pxs3.dtsi324 cdns,phy-dll-delay-sdclk = <21>;
325 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/OK3568_Linux_fs/u-boot/include/configs/
H A Dzipitz2.h89 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=System…
/OK3568_Linux_fs/u-boot/board/bachmann/ot1200/
H A Dot1200_spl.c15 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
/OK3568_Linux_fs/u-boot/board/barco/platinum/
H A Dspl_picon.c30 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
H A Dspl_titanium.c30 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi455 cdns,phy-dll-delay-sdclk = <21>;
456 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-pxs3.dtsi411 cdns,phy-dll-delay-sdclk = <21>;
412 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi585 cdns,phy-dll-delay-sdclk = <21>;
586 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/OK3568_Linux_fs/u-boot/board/gateworks/gw_ventana/
H A Dgw_ventana_spl.c32 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
92 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dmxm8x10.c175 GPIO22 - SDCLK
/OK3568_Linux_fs/u-boot/board/freescale/mx31ads/
H A Dlowlevel_init.S125 /* SDCLK */

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