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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
36 - const: riscv
37 - const: riscv # Simulator only
47 https://riscv.org/specifications/
50 - riscv,sv32
51 - riscv,sv39
52 - riscv,sv48
54 riscv,isa:
59 https://riscv.org/specifications/
62 insensitive, letters in the riscv,isa string must be all
[all …]
/OK3568_Linux_fs/buildroot/package/gdb/10.2/
H A D0007-fix-musl-build-on-riscv.patch4 Subject: [PATCH] fix musl build on riscv
8 ../../gdbserver/linux-riscv-low.cc: In function 'void riscv_fill_fpregset(regcache*, void*)':
9 ../../gdbserver/linux-riscv-low.cc:140:19: error: 'ELF_NFPREG' was not declared in this scope; did …
22 gdb/nat/riscv-linux-tdesc.c | 5 +++++
23 gdbserver/linux-riscv-low.cc | 5 +++++
26 diff --git a/gdb/nat/riscv-linux-tdesc.c b/gdb/nat/riscv-linux-tdesc.c
28 --- a/gdb/nat/riscv-linux-tdesc.c
29 +++ b/gdb/nat/riscv-linux-tdesc.c
39 /* See nat/riscv-linux-tdesc.h. */
42 diff --git a/gdbserver/linux-riscv-low.cc b/gdbserver/linux-riscv-low.cc
[all …]
/OK3568_Linux_fs/buildroot/package/gdb/11.2/
H A D0007-fix-musl-build-on-riscv.patch4 Subject: [PATCH] fix musl build on riscv
8 ../../gdbserver/linux-riscv-low.cc: In function 'void riscv_fill_fpregset(regcache*, void*)':
9 ../../gdbserver/linux-riscv-low.cc:140:19: error: 'ELF_NFPREG' was not declared in this scope; did …
22 gdb/nat/riscv-linux-tdesc.c | 5 +++++
23 gdbserver/linux-riscv-low.cc | 5 +++++
26 diff --git a/gdb/nat/riscv-linux-tdesc.c b/gdb/nat/riscv-linux-tdesc.c
28 --- a/gdb/nat/riscv-linux-tdesc.c
29 +++ b/gdb/nat/riscv-linux-tdesc.c
39 /* See nat/riscv-linux-tdesc.h. */
42 diff --git a/gdbserver/linux-riscv-low.cc b/gdbserver/linux-riscv-low.cc
[all …]
/OK3568_Linux_fs/buildroot/package/gdb/12.1/
H A D0007-fix-musl-build-on-riscv.patch4 Subject: [PATCH] fix musl build on riscv
8 ../../gdbserver/linux-riscv-low.cc: In function 'void riscv_fill_fpregset(regcache*, void*)':
9 ../../gdbserver/linux-riscv-low.cc:140:19: error: 'ELF_NFPREG' was not declared in this scope; did …
22 gdb/nat/riscv-linux-tdesc.c | 5 +++++
23 gdbserver/linux-riscv-low.cc | 5 +++++
26 diff --git a/gdb/nat/riscv-linux-tdesc.c b/gdb/nat/riscv-linux-tdesc.c
28 --- a/gdb/nat/riscv-linux-tdesc.c
29 +++ b/gdb/nat/riscv-linux-tdesc.c
39 /* See nat/riscv-linux-tdesc.h. */
42 diff --git a/gdbserver/linux-riscv-low.cc b/gdbserver/linux-riscv-low.cc
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/
H A DMakefile51 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
52 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
53 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
54 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
58 toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
59 riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
61 KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
62 KBUILD_AFLAGS += -march=$(riscv-march-y)
90 boot := arch/riscv/boot
93 head-y := arch/riscv/kernel/head.o
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
36 compatible = "riscv,cpu-intc";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
53 mmu-type = "riscv,sv39";
55 riscv,isa = "rv64imafdc";
60 compatible = "riscv,cpu-intc";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
77 mmu-type = "riscv,sv39";
79 riscv,isa = "rv64imafdc";
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/boot/dts/kendryte/
H A Dk210.dtsi34 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
35 riscv,isa = "rv64imafdc";
46 compatible = "riscv,cpu-intc";
52 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
53 riscv,isa = "rv64imafdc";
64 compatible = "riscv,cpu-intc";
100 compatible = "riscv,clint0";
110 compatible = "kendryte,k210-plic0", "riscv,plic0";
114 riscv,ndev = <65>;
115 riscv,max-priority = <7>;
/OK3568_Linux_fs/kernel/arch/riscv/kernel/
H A Dcpu.c20 if (!of_device_is_compatible(node, "riscv")) { in riscv_of_processor_hartid()
35 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_of_processor_hartid()
36 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hartid()
56 if (of_device_is_compatible(node, "riscv")) in riscv_of_parent_hartid()
76 if (strcmp(mmu_type, "riscv,sv32") != 0) in print_mmu()
79 if (strcmp(mmu_type, "riscv,sv39") != 0 && in print_mmu()
80 strcmp(mmu_type, "riscv,sv48") != 0) in print_mmu()
113 if (!of_property_read_string(node, "riscv,isa", &isa)) in c_show()
118 && strcmp(compat, "riscv")) in c_show()
H A Dcpufeature.c88 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_fill_hwcap()
89 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); in riscv_fill_hwcap()
139 pr_info("riscv: ISA extensions %s\n", print_str); in riscv_fill_hwcap()
145 pr_info("riscv: ELF capabilities %s\n", print_str); in riscv_fill_hwcap()
/OK3568_Linux_fs/buildroot/board/nezha/patches/uboot/
H A D0001-arch-riscv-dts-sun20i-d1.dtsi-adjust-plic-compatible.patch4 Subject: [PATCH] arch/riscv/dts/sun20i-d1.dtsi: adjust plic compatible to
14 https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd
18 arch/riscv/dts/sun20i-d1.dtsi | 2 +-
21 diff --git a/arch/riscv/dts/sun20i-d1.dtsi b/arch/riscv/dts/sun20i-d1.dtsi
23 --- a/arch/riscv/dts/sun20i-d1.dtsi
24 +++ b/arch/riscv/dts/sun20i-d1.dtsi
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/qemu/qemu/
H A D0001-riscv-Set-5.4-as-minimum-kernel-version-for-riscv32.patch4 Subject: [PATCH] riscv: Set 5.4 as minimum kernel version for riscv32
18 linux-user/riscv/target_syscall.h | 3 ++-
21 diff --git a/linux-user/riscv/target_syscall.h b/linux-user/riscv/target_syscall.h
23 --- a/linux-user/riscv/target_syscall.h
24 +++ b/linux-user/riscv/target_syscall.h
/OK3568_Linux_fs/buildroot/package/uhd/
H A D0003-add-RISC-V-endian-detection.patch4 Subject: [PATCH] msgpack/predef: add riscV support
6 When the target CPU is riscV, msgpack is unable to detect endianness with a list of errors like:
26 .../rpc/msgpack/predef/architecture/riscv.h | 48 +++++++++++++++++++
29 create mode 100644 host/lib/deps/rpclib/include/rpc/msgpack/predef/architecture/riscv.h
39 +#include <rpc/msgpack/predef/architecture/riscv.h>
43 …clude/rpc/msgpack/predef/architecture/riscv.h b/host/lib/deps/rpclib/include/rpc/msgpack/predef/ar…
47 +++ b/host/lib/deps/rpclib/include/rpc/msgpack/predef/architecture/riscv.h
/OK3568_Linux_fs/yocto/poky/meta/conf/machine/
H A Dqemuriscv32.conf5 require conf/machine/include/riscv/qemuriscv.inc
9 PREFERRED_VERSION_openocd-native = "riscv"
10 PREFERRED_VERSION_openocd = "riscv"
12 XVISOR_PLAT = "riscv/virt32"
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-riscv.c116 child = of_get_compatible_child(n, "riscv,cpu-intc"); in riscv_timer_init_dt()
138 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", in riscv_timer_init_dt()
147 "riscv-timer", &riscv_clock_event); in riscv_timer_init_dt()
154 "clockevents/riscv/timer:starting", in riscv_timer_init_dt()
157 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_dt()
162 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml64 riscv,cpu-intc node, which has a riscv node as parent.
66 riscv,ndev:
78 - riscv,ndev
96 riscv,ndev = <10>;
H A Driscv,cpu-intc.txt27 - compatible : "riscv,cpu-intc"
45 compatible = "riscv";
49 compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
/OK3568_Linux_fs/kernel/arch/riscv/include/asm/
H A Dgdb_xml.h13 "qXfer:features:read:riscv-64bit-cpu.xml";
19 "<xi:include href=\"riscv-64bit-cpu.xml\"/>"
25 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
65 "qXfer:features:read:riscv-32bit-cpu.xml";
71 "<xi:include href=\"riscv-32bit-cpu.xml\"/>"
77 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
/OK3568_Linux_fs/yocto/poky/meta/recipes-kernel/lttng/
H A Dlttng-platforms.inc20 # It's also turned off for riscv32 in meta-riscv. See https://github.com/riscv/meta-riscv/blob/mast…
/OK3568_Linux_fs/kernel/drivers/irqchip/
H A Dirq-riscv-intc.c8 #define pr_fmt(fmt) "riscv-intc: " fmt
129 "irqchip/riscv/intc:starting", in riscv_intc_init()
138 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
/OK3568_Linux_fs/yocto/meta-openembedded/meta-oe/recipes-support/opencv/opencv/
H A D0001-Use-Os-to-compile-tinyxml2.cpp.patch6 This workarounds issue [1] seen on riscv with gcc
8 [1] https://github.com/riscv/riscv-gnu-toolchain/issues/624
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/systemd-bootchart/systemd-bootchart/
H A D0001-architecture-Recognise-RISCV-32-RISCV-64.patch4 Subject: [PATCH] architecture: Recognise RISCV-32/RISCV-64
37 +# error "Unrecognized riscv architecture variant"
/OK3568_Linux_fs/yocto/meta-qt5/recipes-qt/qt5/qtwebkit/
H A D0009-Riscv-Add-support-for-riscv.patch4 Subject: [PATCH 1/1] Riscv: Add support for riscv
56 +#if CPU(ARM) || CPU(MIPS) || CPU(SH4) || CPU(ALPHA) || CPU(HPPA) || CPU(RISCV)
79 …S390) || CPU(S390X) || CPU(IA64) || CPU(ALPHA) || CPU(ARM64) || CPU(HPPA) || CPU(ARM) || CPU(RISCV)
/OK3568_Linux_fs/yocto/meta-openembedded/meta-oe/recipes-bsp/flashrom/flashrom/
H A D0001-flashrom-Mark-RISCV-as-non-memory-mapped-I-O-archite.patch4 Subject: [PATCH] flashrom: Mark RISCV as non memory-mapped I/O architecture
23 +ifneq ($(ARCH),$(filter $(ARCH),x86 mips ppc arm sparc arc riscv))
37 +/* Non memory mapped I/O is not supported on RISCV. */
/OK3568_Linux_fs/kernel/drivers/firmware/efi/
H A DMakefile39 riscv-obj-$(CONFIG_EFI) := efi-init.o riscv-runtime.o
40 obj-$(CONFIG_RISCV) += $(riscv-obj-y)
/OK3568_Linux_fs/buildroot/boot/grub2/
H A D0026-efi-Fix-use-after-free-in-halt-reboot-path.patch54 grub-core/kern/riscv/efi/init.c | 3 +++
143 diff --git a/grub-core/kern/riscv/efi/init.c b/grub-core/kern/riscv/efi/init.c
145 --- a/grub-core/kern/riscv/efi/init.c
146 +++ b/grub-core/kern/riscv/efi/init.c

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