| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/ |
| H A D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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| H A D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| H A D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/ |
| H A D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/panel/ |
| H A D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
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| H A D | samsung,ld9040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 spi/spi-controller.yaml
14 - Andrzej Hajda <a.hajda@samsung.com>
17 - $ref: panel-common.yaml#
23 display-timings: true
26 reset-gpios: true
28 vdd3-supply:
31 vci-supply:
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| /OK3568_Linux_fs/kernel/include/linux/reset/ |
| H A D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Simple Reset Controller ops
5 * Based on Allwinner SoCs Reset Controller driver
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
23 * @rcdev: reset controller device base structure
24 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
25 * are set to assert the reset. Note that this says nothing about
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/ |
| H A D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
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| /OK3568_Linux_fs/u-boot/drivers/usb/host/ |
| H A D | ehci-omap.c | 3 * (C) Copyright 2004-2008
11 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/ehci-omap.h>
34 rev = readl(&uhh->rev); in omap_uhh_reset()
36 /* Soft RESET */ in omap_uhh_reset()
37 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); in omap_uhh_reset()
41 /* Wait for soft RESET to complete */ in omap_uhh_reset()
42 while (!(readl(&uhh->syss) & 0x1)) { in omap_uhh_reset()
44 printf("%s: RESET timeout\n", __func__); in omap_uhh_reset()
45 return -1; in omap_uhh_reset()
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| /OK3568_Linux_fs/kernel/drivers/scsi/qla4xxx/ |
| H A D | ql4_83xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
169 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
188 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/c6x/ |
| H A D | clocks.txt | 2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
18 - reg: base address and size of register area
19 - clock-frequency: input clock frequency in hz
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3588-rk806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
12 assigned-clocks = <&cru CLK_SPI2>;
13 assigned-clock-rates = <200000000>;
14 num-cs = <2>;
18 spi-max-frequency = <1000000>;
21 interrupt-parent = <&gpio0>;
24 pinctrl-names = "default", "pmic-power-off";
25 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
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| H A D | rk3588s-rk806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
12 assigned-clocks = <&cru CLK_SPI2>;
13 assigned-clock-rates = <200000000>;
14 num-cs = <2>;
18 spi-max-frequency = <1000000>;
21 interrupt-parent = <&gpio0>;
24 pinctrl-names = "default", "pmic-power-off";
25 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/input/ |
| H A D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /OK3568_Linux_fs/external/security/rk_tee_user/v2/export-ta_arm64/include/mbedtls/ |
| H A D | timing.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
8 * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
14 * http://www.apache.org/licenses/LICENSE-2.0
83 * \param reset If 0, query the elapsed time. Otherwise (re)start the timer.
85 * \return Elapsed time since the previous reset in ms. When
88 * \note To initialize a timer, call this function with reset=1.
94 * the delay since the first reset.
96 unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
101 * \param seconds delay before the "mbedtls_timing_alarmed" flag is set
116 * \param int_ms First (intermediate) delay in milliseconds.
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| /OK3568_Linux_fs/external/security/rk_tee_user/v2/export-ta_arm32/host_include/mbedtls/ |
| H A D | timing.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
8 * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
14 * http://www.apache.org/licenses/LICENSE-2.0
83 * \param reset If 0, query the elapsed time. Otherwise (re)start the timer.
85 * \return Elapsed time since the previous reset in ms. When
88 * \note To initialize a timer, call this function with reset=1.
94 * the delay since the first reset.
96 unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
101 * \param seconds delay before the "mbedtls_timing_alarmed" flag is set
116 * \param int_ms First (intermediate) delay in milliseconds.
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| /OK3568_Linux_fs/external/security/rk_tee_user/v2/export-ta_arm32/include/mbedtls/ |
| H A D | timing.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
8 * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
14 * http://www.apache.org/licenses/LICENSE-2.0
83 * \param reset If 0, query the elapsed time. Otherwise (re)start the timer.
85 * \return Elapsed time since the previous reset in ms. When
88 * \note To initialize a timer, call this function with reset=1.
94 * the delay since the first reset.
96 unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
101 * \param seconds delay before the "mbedtls_timing_alarmed" flag is set
116 * \param int_ms First (intermediate) delay in milliseconds.
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| /OK3568_Linux_fs/external/security/rk_tee_user/v2/export-ta_arm64/host_include/mbedtls/ |
| H A D | timing.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
8 * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
14 * http://www.apache.org/licenses/LICENSE-2.0
83 * \param reset If 0, query the elapsed time. Otherwise (re)start the timer.
85 * \return Elapsed time since the previous reset in ms. When
88 * \note To initialize a timer, call this function with reset=1.
94 * the delay since the first reset.
96 unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
101 * \param seconds delay before the "mbedtls_timing_alarmed" flag is set
116 * \param int_ms First (intermediate) delay in milliseconds.
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/ |
| H A D | rockchip,rk3308-codec.txt | 5 - compatible: "rockchip,rk3308-codec"
6 - reg: The physical base address of the controller and length of memory
8 - rockchip,grf: The phandle of the syscon node for GRF register.
9 - clocks: A list of phandle + clock-specifer pairs, one for each entry in
10 clock-names.
11 - clock-names: It should be "acodec".
12 - resets : Must contain an entry for each entry in reset-names.
13 - reset-names : Must include the following entries: "acodec-reset".
16 - rockchip,enable-all-adcs: This is a boolean type property, that shows whether
19 * grp 0 -- select ADC1 / ADC2
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qlcnic/ |
| H A D | qlcnic_83xx_init.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
11 /* Reset template definitions */
74 u16 delay; member
78 u16 delay;
125 "Need Reset",
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | tegra124.dtsi | 1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
14 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/ |
| H A D | nvidia,tegra114-spi.txt | 4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
12 See ../reset/reset.txt for details.
13 - reset-names : Must include the following entries:
14 - spi
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| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.bootmenu | 2 * (C) Copyright 2011-2012 Pali Rohár <pali.rohar@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 The "bootmenu" command uses U-Boot menu interfaces and provides
14 menu entry invokes an U-Boot command (or a list of commands)
24 bootmenu_delay=<delay>
27 <delay> is the autoboot delay in seconds, after which the first
41 First (optional) argument of the "bootmenu" command is a delay specifier
42 and it overrides the delay value defined by "bootmenu_delay" environment
44 the argument of the "bootmenu" command is not specified, the default delay
45 will be CONFIG_BOOTDELAY. If delay is 0, no menu entries will be shown on
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
13 interrupt-parent = <&lic>;
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