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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllgt215.c42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
51 fN = tmp % info->refclk; in gt215_pll_calc()
54 if (fN >= info->refclk / 2) in gt215_pll_calc()
57 if (fN < info->refclk / 2) in gt215_pll_calc()
59 fN = tmp - (N * info->refclk); in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
75 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
/OK3568_Linux_fs/kernel/drivers/phy/ti/
H A Dphy-dm816x-usb.c56 struct clk *refclk; member
86 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
87 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
133 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_suspend()
144 error = clk_enable(phy->refclk); in dm816x_usb_phy_runtime_resume()
161 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_resume()
236 phy->refclk = devm_clk_get(phy->dev, "refclk"); in dm816x_usb_phy_probe()
237 if (IS_ERR(phy->refclk)) in dm816x_usb_phy_probe()
238 return PTR_ERR(phy->refclk); in dm816x_usb_phy_probe()
239 error = clk_prepare(phy->refclk); in dm816x_usb_phy_probe()
[all …]
H A Dphy-ti-pipe3.c171 struct clk *refclk; member
607 phy->refclk = devm_clk_get(dev, "refclk"); in ti_pipe3_get_clk()
608 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
609 dev_err(dev, "unable to get refclk\n"); in ti_pipe3_get_clk()
610 /* older DTBs have missing refclk in SATA PHY in ti_pipe3_get_clk()
614 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
829 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 in ti_pipe3_probe()
832 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
833 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
855 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_mipi.c208 u32 refclk = priv->ref_clk; in rk_mipi_phy_enable() local
209 u32 remain = refclk; in rk_mipi_phy_enable()
259 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz in rk_mipi_phy_enable()
262 max_prediv = (refclk / (5 * MHz)); in rk_mipi_phy_enable()
263 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); in rk_mipi_phy_enable()
269 debug("%s: Invalid refclk value\n", __func__); in rk_mipi_phy_enable()
273 /* Calculate the best refclk and feedback division value for dphy pll */ in rk_mipi_phy_enable()
275 if ((ddr_clk * i % refclk < remain) && in rk_mipi_phy_enable()
276 (ddr_clk * i / refclk) < max_fbdiv) { in rk_mipi_phy_enable()
278 remain = ddr_clk * i % refclk; in rk_mipi_phy_enable()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dusb3503.txt18 - refclk: Clock used for driving REFCLK signal (optional, if not provided
23 - refclk-frequency: Frequency of the REFCLK signal as defined by REF_SEL
25 REFCLK signal and assume that a value from the primary reference
38 clock-names = "refclk";
H A Docteon-usb.txt24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
54 cavium,refclk-type = "crystal";
/OK3568_Linux_fs/kernel/drivers/phy/xilinx/
H A Dphy-zynqmp.c103 /* Refclk selection parameters */
192 * @refclk: reference clock index
201 unsigned int refclk; member
343 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
350 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
353 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
765 unsigned int refclk; in xpsgtr_xlate() local
794 refclk = args->args[3]; in xpsgtr_xlate()
795 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || in xpsgtr_xlate()
796 !gtr_dev->refclk_sscs[refclk]) { in xpsgtr_xlate()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dgma_display.h44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
91 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
92 extern void gma_clock(int refclk, struct gma_clock_t *clock);
97 struct drm_crtc *crtc, int target, int refclk,
H A Dcdv_intel_display.c24 int refclk, struct gma_clock_t *best_clock);
364 int refclk) in cdv_intel_limit() argument
372 if (refclk == 96000) in cdv_intel_limit()
378 if (refclk == 27000) in cdv_intel_limit()
383 if (refclk == 27000) in cdv_intel_limit()
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
396 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
402 int refclk, in cdv_intel_find_dp_pll() argument
410 switch (refclk) { in cdv_intel_find_dp_pll()
447 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
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H A Doaktrail_crtc.c38 int refclk, struct gma_clock_t *best_clock);
42 int refclk, struct gma_clock_t *best_clock);
81 int refclk) in mrst_limit() argument
110 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
111 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
113 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
125 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
150 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
178 * Returns a set of divisors for the desired target clock with the given refclk,
183 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/arc/
H A Demac_rockchip.c32 struct clk *refclk; member
147 priv->refclk = devm_clk_get(dev, "macref"); in emac_rockchip_probe()
148 if (IS_ERR(priv->refclk)) { in emac_rockchip_probe()
150 PTR_ERR(priv->refclk)); in emac_rockchip_probe()
151 err = PTR_ERR(priv->refclk); in emac_rockchip_probe()
155 err = clk_prepare_enable(priv->refclk); in emac_rockchip_probe()
195 err = clk_set_rate(priv->refclk, 50000000); in emac_rockchip_probe()
241 clk_disable_unprepare(priv->refclk); in emac_rockchip_probe()
255 clk_disable_unprepare(priv->refclk); in emac_rockchip_remove()
/OK3568_Linux_fs/kernel/arch/mips/bcm63xx/
H A Dclk.c421 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
422 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
438 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
439 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
452 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
466 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
480 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
495 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
496 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
514 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/
H A Dcpts.c571 err = clk_enable(cpts->refclk); in cpts_register()
592 clk_disable(cpts->refclk); in cpts_register()
612 clk_disable(cpts->refclk); in cpts_unregister()
621 freq = clk_get_rate(cpts->refclk); in cpts_calc_mult_shift()
662 refclk_np = of_get_child_by_name(node, "cpts-refclk-mux"); in cpts_of_mux_clk_setup()
664 /* refclk selection supported not for all SoCs */ in cpts_of_mux_clk_setup()
772 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts"); in cpts_create()
773 if (IS_ERR(cpts->refclk)) in cpts_create()
775 cpts->refclk = devm_clk_get(dev, "cpts"); in cpts_create()
777 if (IS_ERR(cpts->refclk)) { in cpts_create()
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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Dsmsc.c48 struct clk *refclk; member
265 clk_disable_unprepare(priv->refclk); in smsc_phy_remove()
266 clk_put(priv->refclk); in smsc_phy_remove()
288 priv->refclk = clk_get_optional(dev, NULL); in smsc_phy_probe()
289 if (IS_ERR(priv->refclk)) in smsc_phy_probe()
290 return dev_err_probe(dev, PTR_ERR(priv->refclk), in smsc_phy_probe()
293 ret = clk_prepare_enable(priv->refclk); in smsc_phy_probe()
297 ret = clk_set_rate(priv->refclk, 50 * 1000 * 1000); in smsc_phy_probe()
299 clk_disable_unprepare(priv->refclk); in smsc_phy_probe()
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c442 struct clk *refclk = NULL; in rk3528_combphy_cfg() local
449 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3528_combphy_cfg()
450 refclk = priv->clks[i].clk; in rk3528_combphy_cfg()
455 if (!refclk) { in rk3528_combphy_cfg()
456 dev_err(priv->dev, "No refclk found\n"); in rk3528_combphy_cfg()
501 rate = clk_get_rate(refclk); in rk3528_combphy_cfg()
564 { .id = "refclk" },
579 struct clk *refclk = NULL; in rk3562_combphy_cfg() local
586 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3562_combphy_cfg()
587 refclk = priv->clks[i].clk; in rk3562_combphy_cfg()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
30 refclk-frequency = <24000000>;
32 refclk-type = "crystal";
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dberlin2cd.dtsi51 refclk: oscillator { label
389 clocks = <&refclk>;
390 clock-names = "refclk";
446 clocks = <&refclk>;
453 clocks = <&refclk>;
461 clocks = <&refclk>;
486 clocks = <&refclk>;
497 clocks = <&refclk>;
507 clocks = <&refclk>;
532 clocks = <&refclk>;
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/OK3568_Linux_fs/kernel/drivers/clk/berlin/
H A Dbg2.c90 REFCLK, VIDEO_EXT0, enumerator
103 [REFCLK] = "refclk",
516 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2_clock_setup()
518 clk_names[REFCLK] = __clk_get_name(clk); in berlin2_clock_setup()
530 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
535 clk_names[MEMPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
540 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
549 clk_names[REFCLK], avpll_flags, 0); in berlin2_clock_setup()
562 clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK | in berlin2_clock_setup()
577 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
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H A Dbg2q.c45 REFCLK, enumerator
52 [REFCLK] = "refclk",
313 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2q_clock_setup()
315 clk_names[REFCLK] = __clk_get_name(clk); in berlin2q_clock_setup()
321 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
326 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml77 "^pll[0|1]-refclk$":
120 "^refclk-dig$":
188 pll0-refclk {
195 pll1-refclk {
202 cmn-refclk-dig-div {
212 refclk-dig {
/OK3568_Linux_fs/kernel/sound/soc/meson/
H A Daxg-spdifin.c55 struct clk *refclk; member
121 ret = clk_prepare_enable(priv->refclk); in axg_spdifin_startup()
140 clk_disable_unprepare(priv->refclk); in axg_spdifin_shutdown()
193 ret = clk_set_rate(priv->refclk, priv->conf->ref_rate); in axg_spdifin_sample_mode_config()
203 rate = clk_get_rate(priv->refclk); in axg_spdifin_sample_mode_config()
489 priv->refclk = devm_clk_get(dev, "refclk"); in axg_spdifin_probe()
490 if (IS_ERR(priv->refclk)) { in axg_spdifin_probe()
491 ret = PTR_ERR(priv->refclk); in axg_spdifin_probe()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dtc358767.c261 struct clk *refclk; member
457 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ in tc_pllupdate()
463 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) in tc_pxl_pll_en() argument
477 refclk); in tc_pxl_pll_en()
482 * refclk / ext_pre_div should be in the 1 to 200 MHz range. in tc_pxl_pll_en()
483 * We don't allow any refclk > 200 MHz, only check lower bounds. in tc_pxl_pll_en()
485 if (refclk / ext_div[i_pre] < 1000000) in tc_pxl_pll_en()
494 do_div(tmp, refclk); in tc_pxl_pll_en()
501 clk = (refclk / ext_div[i_pre] / div) * mul; in tc_pxl_pll_en()
503 * refclk * mul / (ext_pre_div * pre_div) in tc_pxl_pll_en()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dkeystone-k2hk-evm.dts25 clock-output-names = "refclk-sys";
32 clock-output-names = "refclk-pass";
39 clock-output-names = "refclk-arm";
46 clock-output-names = "refclk-ddr3a";
53 clock-output-names = "refclk-ddr3b";
/OK3568_Linux_fs/kernel/drivers/phy/
H A Dphy-pistachio-usb.c38 unsigned int refclk; member
68 p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT); in pistachio_usb_phy_power_on()
71 if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) { in pistachio_usb_phy_power_on()
160 ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk", in pistachio_usb_phy_probe()
161 &p_phy->refclk); in pistachio_usb_phy_probe()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c1186 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1188 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1189 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1190 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1195 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1196 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1197 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1202 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1203 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
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