Searched +full:r8a7795 +full:- +full:rst (Results 1 – 16 of 16) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"7 title: Renesas R-Car and RZ/G Reset Controller10 - Geert Uytterhoeven <geert+renesas@glider.be>11 - Magnus Damm <magnus.damm@gmail.com>14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the16 - Latching of the levels on mode pins when PRESET# is negated,17 - Mode monitoring register,[all …]
1 // SPDX-License-Identifier: GPL-2.03 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver11 #include <linux/soc/renesas/rcar-rst.h>45 /* RZ/G1 is handled like R-Car Gen2 */46 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },47 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },48 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },49 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },50 { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },51 /* RZ/G2 is handled like R-Car Gen3 */[all …]
1 # SPDX-License-Identifier: GPL-2.03 obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o6 obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o7 obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o8 obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o9 obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o10 obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o11 obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o12 obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o13 obj-$(CONFIG_SYSC_R8A774E1) += r8a774e1-sysc.o[all …]
2 * Device Tree Source for the r8a7795 SoC11 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/power/r8a7795-sysc.h>16 compatible = "renesas,r8a7795";17 #address-cells = <2>;18 #size-cells = <2>;32 compatible = "arm,psci-1.0", "arm,psci-0.2";37 #address-cells = <1>;38 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car H3 (R8A77951) SoC8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a7795-sysc.h>15 compatible = "renesas,r8a7795";16 #address-cells = <2>;17 #size-cells = <2>;36 compatible = "fixed-clock";37 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset6 * Copyright (C) 2018-2019 Renesas Electronics Corp.8 * Based on clk-rcar-gen3.c16 #include <linux/soc/renesas/rcar-rst.h>19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>21 #include "renesas-cpg-mssr.h"22 #include "rcar-gen3-cpg.h"128 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */129 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Based on r8a7795-cpg-mssr.c16 #include <linux/soc/renesas/rcar-rst.h>18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>20 #include "renesas-cpg-mssr.h"21 #include "rcar-gen3-cpg.h"124 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),125 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),126 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),127 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Based on r8a7795-cpg-mssr.c16 #include <linux/clk-provider.h>24 #include <linux/soc/renesas/rcar-rst.h>26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>28 #include "renesas-cpg-mssr.h"172 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_r8a779a0_cpg_clk_register()176 switch (core->type) { in rcar_r8a779a0_cpg_clk_register()178 div = cpg_pll_config->extal_div; in rcar_r8a779a0_cpg_clk_register()182 mult = cpg_pll_config->pll1_mult; in rcar_r8a779a0_cpg_clk_register()[all …]
1 // SPDX-License-Identifier: GPL-2.08 * Based on r8a7795-cpg-mssr.c16 #include <linux/soc/renesas/rcar-rst.h>19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>21 #include "renesas-cpg-mssr.h"22 #include "rcar-gen3-cpg.h"127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2017-2018 Cogent Embedded Inc.7 * Based on r8a7795-cpg-mssr.c12 #include <linux/clk-provider.h>16 #include <linux/soc/renesas/rcar-rst.h>18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>20 #include "renesas-cpg-mssr.h"21 #include "rcar-gen3-cpg.h"125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2018-2019 Renesas Electronics Corp.7 * Based on r8a7795-cpg-mssr.c16 #include <linux/soc/renesas/rcar-rst.h>18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>20 #include "renesas-cpg-mssr.h"21 #include "rcar-gen3-cpg.h"136 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),137 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),138 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),[all …]
1 // SPDX-License-Identifier: GPL-2.08 * Based on r8a7795-cpg-mssr.c17 #include <linux/soc/renesas/rcar-rst.h>19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>21 #include "renesas-cpg-mssr.h"22 #include "rcar-gen3-cpg.h"125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),135 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),136 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),137 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),[all …]
1 // SPDX-License-Identifier: GPL-2.03 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software6 * Copyright (C) 2016-2019 Glider bvba7 * Copyright (C) 2018-2019 Renesas Electronics Corp.9 * Based on r8a7795-cpg-mssr.c19 #include <linux/soc/renesas/rcar-rst.h>21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>23 #include "renesas-cpg-mssr.h"24 #include "rcar-gen3-cpg.h"130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Based on r8a7795-cpg-mssr.c15 #include <linux/soc/renesas/rcar-rst.h>17 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>19 #include "renesas-cpg-mssr.h"20 #include "rcar-gen3-cpg.h"124 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),142 DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),143 DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),[all …]
2 * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver11 * SPDX-License-Identifier: GPL-2.0+15 #include <clk-uclass.h>21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>33 * If the registers exist, these are valid for SH-Mobile, R-Mobile,34 * R-Car Gen2, R-Car Gen3, and RZ/G1.35 * These are NOT valid for R-Car Gen1 and RZ/A1!63 #define RMSTPCR(i) (smstpcr[i] - 0x20)86 * - Clock outputs exported to DT[all …]
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