Searched +full:r8a7795 +full:- +full:lvds (Results 1 – 19 of 19) sorted by relevance
1 * Renesas R-Car Display Unit (DU)5 - compatible: must be one of the following.6 - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU7 - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU8 - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU9 - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU10 - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU11 - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU12 - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU13 - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas R-Car LVDS Encoder10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders[all …]
1 // SPDX-License-Identifier: GPL-2.03 * rcar_du_of_lvds_r8a7795.dts - Legacy LVDS DT bindings conversion for R8A77958 /dts-v1/;12 #address-cells = <2>;13 #size-cells = <2>;15 lvds@feb90000 {16 compatible = "renesas,r8a7795-lvds";20 #address-cells = <1>;21 #size-cells = <0>;40 remote-endpoint = <&lvds0_input>;
1 // SPDX-License-Identifier: GPL-2.03 * rcar_du_of.c - Legacy DT bindings compatibility23 /* -----------------------------------------------------------------------------39 .compatible = "renesas,du-" #soc, \59 return -ENODEV; in rcar_du_of_apply_overlay()62 return of_overlay_fdt_apply(dtb->begin, dtb->end - dtb->begin, in rcar_du_of_apply_overlay()72 int ret = -ENOMEM; in rcar_du_of_add_property()76 return -ENOMEM; in rcar_du_of_add_property()78 prop->name = kstrdup(name, GFP_KERNEL); in rcar_du_of_add_property()79 if (!prop->name) in rcar_du_of_add_property()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * rcar_du_drv.c -- R-Car Display Unit DRM driver5 * Copyright (C) 2013-2015 Renesas Electronics Corporation32 /* -----------------------------------------------------------------------------44 * R8A774[34] has one RGB output and one LVDS output87 * R8A77470 has two RGB outputs, one LVDS output, and114 * R8A774A1 has one RGB output, one LVDS output and one HDMI143 * R8A774B1 has one RGB output, one LVDS output and one HDMI170 * R8A774C0 has one RGB output and two LVDS outputs198 * R8A774E1 has one RGB output, one LVDS output and one HDMI[all …]
1 // SPDX-License-Identifier: GPL-2.03 * rcar_lvds.c -- R-Car LVDS Encoder5 * Copyright (C) 2013-2018 Renesas Electronics Corporation47 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */56 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);86 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) in rcar_lvds_write() argument88 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()91 /* -----------------------------------------------------------------------------97 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector); in rcar_lvds_connector_get_modes() local[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * rcar_du_crtc.c -- R-Car Display Unit CRTCs5 * Copyright (C) 2013-2015 Renesas Electronics Corporation37 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_read()39 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); in rcar_du_crtc_read()44 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_write()46 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); in rcar_du_crtc_write()51 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_clr()53 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_clr()54 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr()[all …]
2 * Device Tree Source for the r8a7795 SoC11 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/power/r8a7795-sysc.h>16 compatible = "renesas,r8a7795";17 #address-cells = <2>;18 #size-cells = <2>;32 compatible = "arm,psci-1.0", "arm,psci-0.2";37 #address-cells = <1>;38 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car H3 (R8A77951) SoC8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a7795-sysc.h>15 compatible = "renesas,r8a7795";16 #address-cells = <2>;17 #size-cells = <2>;36 compatible = "fixed-clock";37 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset6 * Copyright (C) 2018-2019 Renesas Electronics Corp.8 * Based on clk-rcar-gen3.c16 #include <linux/soc/renesas/rcar-rst.h>19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>21 #include "renesas-cpg-mssr.h"22 #include "rcar-gen3-cpg.h"128 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */129 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Based on r8a7795-cpg-mssr.c16 #include <linux/soc/renesas/rcar-rst.h>18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>20 #include "renesas-cpg-mssr.h"21 #include "rcar-gen3-cpg.h"124 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),125 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),126 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),127 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),[all …]
1 // SPDX-License-Identifier: GPL-2.08 * Based on r8a7795-cpg-mssr.c16 #include <linux/soc/renesas/rcar-rst.h>19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>21 #include "renesas-cpg-mssr.h"22 #include "rcar-gen3-cpg.h"127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2017-2018 Cogent Embedded Inc.7 * Based on r8a7795-cpg-mssr.c12 #include <linux/clk-provider.h>16 #include <linux/soc/renesas/rcar-rst.h>18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>20 #include "renesas-cpg-mssr.h"21 #include "rcar-gen3-cpg.h"125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2018-2019 Renesas Electronics Corp.7 * Based on r8a7795-cpg-mssr.c16 #include <linux/soc/renesas/rcar-rst.h>18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>20 #include "renesas-cpg-mssr.h"21 #include "rcar-gen3-cpg.h"136 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),137 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),138 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),[all …]
1 // SPDX-License-Identifier: GPL-2.08 * Based on r8a7795-cpg-mssr.c17 #include <linux/soc/renesas/rcar-rst.h>19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>21 #include "renesas-cpg-mssr.h"22 #include "rcar-gen3-cpg.h"125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),135 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),136 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),137 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),[all …]
1 // SPDX-License-Identifier: GPL-2.03 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software6 * Copyright (C) 2016-2019 Glider bvba7 * Copyright (C) 2018-2019 Renesas Electronics Corp.9 * Based on r8a7795-cpg-mssr.c19 #include <linux/soc/renesas/rcar-rst.h>21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>23 #include "renesas-cpg-mssr.h"24 #include "rcar-gen3-cpg.h"130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Based on r8a7795-cpg-mssr.c15 #include <linux/soc/renesas/rcar-rst.h>17 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>19 #include "renesas-cpg-mssr.h"20 #include "rcar-gen3-cpg.h"124 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),142 DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),143 DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),[all …]
2 * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver11 * SPDX-License-Identifier: GPL-2.0+15 #include <clk-uclass.h>21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>33 * If the registers exist, these are valid for SH-Mobile, R-Mobile,34 * R-Car Gen2, R-Car Gen3, and RZ/G1.35 * These are NOT valid for R-Car Gen1 and RZ/A1!63 #define RMSTPCR(i) (smstpcr[i] - 0x20)86 * - Clock outputs exported to DT[all …]
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