Searched +full:px30 +full:- +full:dsi +full:- +full:dphy (Results 1 – 12 of 12) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes10 - Heiko Stuebner <heiko@sntech.de>13 "#phy-cells":18 - rockchip,px30-dsi-dphy19 - rockchip,rk3128-dsi-dphy20 - rockchip,rk3368-dsi-dphy[all …]
1 Rockchip specific extensions to the Synopsys Designware MIPI DSI5 - #address-cells: Should be <1>.6 - #size-cells: Should be <0>.7 - compatible: one of8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"11 - reg: Represent the physical address range of the controller.12 - interrupts: Represent the controller's interrupt to the CPU(s).13 - clocks, clock-names: Phandles to the controller's pll reference[all …]
5 - compatible: matching the soc type, one of6 - "rockchip,rk3288-lvds";7 - "rockchip,px30-lvds";9 - reg: physical base address of the controller and length11 - clocks: must include clock specifiers corresponding to entries in the12 clock-names property.13 - clock-names: must contain "pclk_lvds"15 - avdd1v0-supply: regulator phandle for 1.0V analog power16 - avdd1v8-supply: regulator phandle for 1.8V analog power17 - avdd3v3-supply: regulator phandle for 3.3V analog power[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Chris Zhong <zyw@rock-chips.com>6 * Nickey Yang <nickey.yang@rock-chips.com>41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)225 PX30, enumerator285 /* dual-channel */289 /* optional external dphy */[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Author: Wyon Bi <bivvy.bi@rock-chips.com>11 #include <linux/clk-provider.h>19 #include <linux/phy/phy-mipi-dphy.h>201 PX30, enumerator312 orig = readl(inno->phy_base + reg); in phy_update_bits()315 writel(tmp, inno->phy_base + reg); in phy_update_bits()323 orig = readl(inno->host_base + reg); in host_update_bits()326 writel(tmp, inno->host_base + reg); in host_update_bits()332 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()[all …]
2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd4 * SPDX-License-Identifier: GPL-2.0+19 #include <asm/arch-rockchip/clock.h>163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)225 /* Non-SNPS PHY */247 struct mipi_dphy dphy; member254 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) in dsi_write() argument256 writel(val, dsi->base + reg); in dsi_write()259 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) in dsi_read() argument261 return readl(dsi->base + reg); in dsi_read()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/px30-cru.h>7 #include <dt-bindings/display/media-bus-format.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/interrupt-controller/irq.h>11 #include <dt-bindings/pinctrl/rockchip.h>12 #include <dt-bindings/power/px30-power.h>13 #include <dt-bindings/soc/rockchip,boot-mode.h>14 #include <dt-bindings/soc/rockchip-system-status.h>[all …]
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