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/OK3568_Linux_fs/kernel/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-fm-tx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-tx-controls:
15 .. _fm-tx-control-id:
27 step are driver-specific.
34 to 31 pre-defined programme types.
52 programme-related information or any other text. In these cases,
103 receiver-generated distortion and prevent overmodulation.
107 useconds. Step and range are driver-specific.
111 are driver-specific.
121 range and step are driver-specific.
[all …]
H A Dext-ctrls-fm-rx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-rx-controls:
13 .. _fm-rx-control-id:
27 Gets RDS Programme Type field. This encodes up to 31 pre-defined
45 wishes to transmit longer PS names, programme-related information or
70 enum v4l2_deemphasis -
71 Configures the de-emphasis value for reception. A de-emphasis filter
75 values for de-emphasis. Here they are:
79 .. flat-table::
80 :header-rows: 0
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/clk-provider.h>
30 #include <linux/phy/phy-rockchip-usbdp.h>
57 /* u2phy-grf */
61 /* usb-grf */
65 /* usbdpphy-grf */
71 /* vo-grf */
127 bool hs; /* flag for high-speed */
146 /* voltage swing 0, pre-emphasis 0->3 */
154 /* voltage swing 1, pre-emphasis 0->2 */
[all …]
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0
354 /* voltage swing 0, pre-emphasis 0->3 */
362 /* voltage swing 1, pre-emphasis 0->2 */
369 /* voltage swing 2, pre-emphasis 0->1 */
375 /* voltage swing 3, pre-emphasis 0 */
382 /* voltage swing 0, pre-emphasis 0->3 */
390 /* voltage swing 1, pre-emphasis 0->2 */
397 /* voltage swing 2, pre-emphasis 0->1 */
403 /* voltage swing 3, pre-emphasis 0 */
410 /* voltage swing 0, pre-emphasis 0->3 */
[all …]
H A Dphy-rockchip-inno-usb3.c104 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
105 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
106 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
107 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
157 unsigned int tmp = desired ? reg->dvalue : reg->rvalue; in param_write()
160 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
161 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
162 ret = regmap_write(base, reg->offset, val); in param_write()
173 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); in param_exped()
175 ret = regmap_read(base, reg->offset, &orig); in param_exped()
[all …]
H A Dphy-rockchip-naneng-edp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
92 { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
93 { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
94 { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
103 amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltage()
104 amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltage()
105 emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltage()
109 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
112 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <generic-phy.h>
24 #include <linux/usb/phy-rockchip-usbdp.h>
51 * struct reg_sequence - An individual write from a sequence of writes.
67 /* u2phy-grf */
71 /* usb-grf */
75 /* usbdpphy-grf */
125 bool hs; /* flag for high-speed */
143 /* voltage swing 0, pre-emphasis 0->3 */
151 /* voltage swing 1, pre-emphasis 0->2 */
[all …]
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <generic-phy.h>
353 /* voltage swing 0, pre-emphasis 0->3 */
361 /* voltage swing 1, pre-emphasis 0->2 */
368 /* voltage swing 2, pre-emphasis 0->1 */
374 /* voltage swing 3, pre-emphasis 0 */
381 /* voltage swing 0, pre-emphasis 0->3 */
389 /* voltage swing 1, pre-emphasis 0->2 */
396 /* voltage swing 2, pre-emphasis 0->1 */
402 /* voltage swing 3, pre-emphasis 0 */
[all …]
H A Dphy-rockchip-inno-usb3.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on phy-rockchip-inno-usb3.c in Linux Kernel.
12 #include <generic-phy.h>
89 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
90 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
91 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
92 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
132 unsigned int tmp = desired ? reg->dvalue : reg->rvalue; in param_write()
135 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
136 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
[all …]
H A Dphy-rockchip-naneng-edp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
10 #include <generic-phy.h>
86 { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
87 { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
88 { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
97 amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltage()
98 amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltage()
99 emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltage()
103 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
[all …]
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
H A Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dgeneric-phy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
47 * @pre:
49 * Pre-emphasis levels, as specified by DisplayPort specification, to be
54 unsigned int pre[4]; member
59 * Flag indicating, whether or not to enable spread-spectrum clocking.
86 * and pre-emphasis to requested values. Only lanes specified
/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
49 * @pre:
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
56 unsigned int pre[4]; member
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
88 * and pre-emphasis to requested values. Only lanes specified
/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Ddisplayport.h4 * SPDX-License-Identifier: GPL-2.0
134 /* pre-emphasis: L0, L1, L2, L3 */
169 /* pre-emphasis: L0, L1, L2, L3 */
204 /* pre-emphasis: L0, L1, L2, L3 */
239 /* pre-emphasis: L0, L1, L2, L3 */
295 return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; in tegra_dp_is_max_vs()
300 return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; in tegra_dp_is_max_pe()
/OK3568_Linux_fs/u-boot/board/hisilicon/poplar/
H A Dpoplar.c3 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
5 * SPDX-License-Identifier: GPL-2.0+
64 gd->ram_size = get_ram_size(NULL, 0x80000000); in dram_init()
85 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; in dram_init_banksize()
86 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; in dram_init_banksize()
94 /* close EOP pre-emphasis. open data pre-emphasis */ in usb2_phy_config()
/OK3568_Linux_fs/buildroot/dl/sox/git/src/
H A Ddeemph.plt1 # 15/50us EIAJ de-emphasis filter for CD/DAT
10 # This implements the inverse filter of the optional pre-emphasis stage
17 # The commonly used solution at that time was to 'pre-emphasize' the
18 # trebles to have a better signal-noise-ratio. That is trebles were
31 # | 20dB / decade ->/ |
41 # filter automatically, the cd-rom drives or cd burners used by digital
54 OmegaU = 1. / 15e-6
59 H0 = V0 - 1.
61 A1 = (B - 1.) / (B + 1.)
62 B0 = (1. + (1. - A1) * H0 / 2.)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
142 * To configure the source termination and pre-emphasis appropriately in sti_hdmi_tx3g4c28phy_start()
168 * Default, power up the serializer with no pre-emphasis or in sti_hdmi_tx3g4c28phy_start()
192 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_stop()
201 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_stop()
202 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_stop()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588s-evb8-lp4x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "dt-bindings/usb/pd.h"
9 #include "rk3588s-evb.dtsi"
10 #include "rk3588-rk806-single.dtsi"
13 combophy_avdd0v85: combophy-avdd0v85 {
14 compatible = "regulator-fixed";
15 regulator-name = "combophy_avdd0v85";
16 regulator-boot-on;
17 regulator-always-on;
18 regulator-min-microvolt = <850000>;
[all …]
H A Drk3588s-evb1-lp4x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "dt-bindings/usb/pd.h"
9 #include "rk3588s-evb.dtsi"
10 #include "rk3588s-rk806-dual.dtsi"
13 aw883xx_sound: aw883x-sound {
15 compatible = "rockchip,multicodecs-card";
16 rockchip,card-name = "rockchip-aw883xx";
18 rockchip,mclk-fs = <256>;
23 combophy_avdd0v85: combophy-avdd0v85 {
24 compatible = "regulator-fixed";
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/samsung/
H A Dphy-exynos-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
89 exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); in exynos5440_pcie_phy_init()
92 exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); in exynos5440_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); in exynos5440_pcie_phy_init()
96 exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); in exynos5440_pcie_phy_init()
99 exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); in exynos5440_pcie_phy_init()
101 /* set TX Pre-emphasis Level Control for lane 0 to minimum */ in exynos5440_pcie_phy_init()
102 exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL); in exynos5440_pcie_phy_init()
105 exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS); in exynos5440_pcie_phy_init()
106 exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR); in exynos5440_pcie_phy_init()
[all …]
/OK3568_Linux_fs/buildroot/board/hardkernel/odroidxu4/
H A Dboot.ini1 ODROIDXU-UBOOT-CONFIG
3 # U-Boot Parameters
9 …c 0:1 0x40008000 zImage; load mmc 0:1 0x44000000 exynos5422-odroidxu4.dtb; bootz 0x40008000 - 0x44…
22 # TMDS data pre-emphasis level control.
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/perl-cross/files/
H A DREADME.md1 **perl-cross** provides configure script, top-level Makefile
3 with the primary emphasis on cross-compiling the source.
5 # Get perl and perl-cross sources
6 curl -L -O http://www.cpan.org/src/5.0/perl-5.24.1.tar.gz
7 curl -L -O https://github.com/arsv/perl-cross/releases/download/1.1.3/perl-cross-1.1.3.tar.gz
9 # Unpack perl-cross over perl, overwriting Makefile
10 tar -zxf perl-5.24.1.tar.gz
11 cd perl-5.24.1
12 tar --strip-components=1 -zxf ../perl-cross-1.1.3.tar.gz
15 ./configure --target=arm-linux-gnueabi --prefix=/usr -Duseshrplib
[all …]
/OK3568_Linux_fs/kernel/include/sound/
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
[all …]

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