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/OK3568_Linux_fs/kernel/drivers/scsi/isci/
H A Dremote_node_context.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
61 * the remote node context in the silicon. It exists to model and manage
62 * the remote node context in the silicon.
100 * @SCI_RNC_INVALIDATING: transition state that will post an RNC invalidate to
104 * @SCI_RNC_RESUMING: transition state that will post an RNC resume to the
148 RNC_DEST_SUSPENDED, /* Set when suspend during post/invalidate */
155 * struct sci_remote_node_context - This structure contains the data
158 * the silicon RNC.
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/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dt1042si-post.dtsi2 * T1042 Silicon/SoC Device Tree Source (post include)
35 #include "t1040si-post.dtsi"
H A Dt2080si-post.dtsi2 * T2080 Silicon/SoC Device Tree Source (post include)
35 /include/ "t2081si-post.dtsi"
38 /include/ "qoriq-sata2-0.dtsi"
40 fsl,iommu-parent = <&pamu1>;
41 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
44 /include/ "qoriq-sata2-1.dtsi"
46 fsl,iommu-parent = <&pamu1>;
47 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
54 #address-cells = <2>;
55 #size-cells = <2>;
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H A Db4420si-post.dtsi2 * B4420 Silicon/SoC Device Tree Source (post include)
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
43 dcsr-epu@0 {
44 compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
46 dcsr-npc {
47 compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
49 dcsr-dpaa@9000 {
50 compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
52 dcsr-ocn@11000 {
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H A Dt1024si-post.dtsi2 * T1024 Silicon/SoC Device Tree Source (post include)
35 #include "t1023si-post.dtsi"
44 #address-cells = <1>;
45 #size-cells = <1>;
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
59 compatible = "fsl,t1024-diu", "fsl,diu";
66 qeic: interrupt-controller@80 {
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H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8641 Silicon/SoC Device Tree Source (post include)
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
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H A Dmpc8548si-post.dtsi2 * MPC8548 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8540-pci";
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H A Dbsc9131si-post.dtsi2 * BSC9131 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
46 compatible = "fsl,bsc9131-immr", "simple-bus";
47 bus-frequency = <0>; // Filled out by uboot.
49 ecm-law@0 {
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H A Db4860si-post.dtsi2 * B4860 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
51 #address-cells = <2>;
52 #size-cells = <2>;
53 cell-index = <1>;
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H A Dp1020si-post.dtsi2 * P1020/P1011 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
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H A Dc293si-post.dtsi2 * C293 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
44 compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
[all …]
H A Dmpc8572si-post.dtsi2 * MPC8572 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
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H A Dbsc9132si-post.dtsi2 * BSC9132 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
45 compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
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H A Dmpc8544si-post.dtsi2 * MPC8544 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_hws_hw_training.c4 * SPDX-License-Identifier: GPL-2.0
28 if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) || in ddr3_if_ecc_enabled()
29 DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) in ddr3_if_ecc_enabled()
40 if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) { in ddr3_pre_algo_config()
48 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) || in ddr3_pre_algo_config()
49 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) { in ddr3_pre_algo_config()
74 printf("DDR3 Post Run Alg - FAILED 0x%x\n", status); in ddr3_post_algo_config()
79 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) || in ddr3_post_algo_config()
80 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) { in ddr3_post_algo_config()
99 printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status); in ddr3_hws_hw_training()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/ast/
H A Dast_main.c14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
70 struct device_node *np = dev->pdev->dev.of_node; in ast_detect_config_mode()
75 ast->config_mode = ast_use_defaults; in ast_detect_config_mode()
78 /* Check if we have device-tree properties */ in ast_detect_config_mode()
79 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", in ast_detect_config_mode()
82 ast->config_mode = ast_use_dt; in ast_detect_config_mode()
83 drm_info(dev, "Using device-tree for configuration\n"); in ast_detect_config_mode()
88 if (dev->pdev->device != PCI_CHIP_AST2000) in ast_detect_config_mode()
102 /* P2A works, grab silicon revision */ in ast_detect_config_mode()
103 ast->config_mode = ast_use_p2a; in ast_detect_config_mode()
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
32 #define MII_SREVISION 0x16 /* Silicon revision */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
32 #define MII_SREVISION 0x16 /* Silicon revision */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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/OK3568_Linux_fs/yocto/meta-rockchip/recipes-devtools/rtl-tools/files/
H A Dhciattach.c3 * BlueZ - Bluetooth protocol stack for Linux
5 * Copyright (C) 2000-2001 Qualcomm Incorporated
6 * Copyright (C) 2002-2003 Maxim Krasnyansky <maxk@qualcomm.com>
7 * Copyright (C) 2002-2010 Marcel Holtmann <marcel@holtmann.org>
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
65 int (*post) (int fd, struct uart_t *u, struct termios *ti); member
153 return -errno; in set_speed()
156 return -errno; in set_speed()
159 return -errno; in set_speed()
173 return -1; in read_hci_event()
[all …]
/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
32 #define MII_SREVISION 0x16 /* Silicon revision */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
/OK3568_Linux_fs/u-boot/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
20 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
21 #define MII_STAT1000 0x0a /* 1000BASE-T status */
27 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
29 #define MII_SREVISION 0x16 /* Silicon revision */
52 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
55 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
57 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
60 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
/OK3568_Linux_fs/kernel/drivers/media/tuners/
H A Dtda18271-priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 tda18271-priv.h - private header for the NXP TDA18271 silicon tuner
17 #include "tuner-i2c.h"
28 #define R_CPD 0x08 /* Cal Post-Divider byte */
32 #define R_MPD 0x0c /* Main Post-Divider byte */
62 /*---------------------------------------------------------------------*/
121 /*---------------------------------------------------------------------*/
162 /*---------------------------------------------------------------------*/
196 /*---------------------------------------------------------------------*/
/OK3568_Linux_fs/external/xserver/xkb/
H A DxkbActions.c2 Copyright (c) 1993 by Silicon Graphics Computer Systems, Inc.
9 documentation, and that the name of Silicon Graphics not be
12 Silicon Graphics makes no representation about the suitability
16 SILICON GRAPHICS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
18 AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SILICON
28 #include <dix-config.h>
59 if (xkbPrivPtr->unwrapProc) in xkbUnwrapProc()
60 xkbPrivPtr->unwrapProc = NULL; in xkbUnwrapProc()
90 (!(xkb->ctrls->enabled_ctrls & XkbMouseKeysMask))) { in _FixUpAction()
94 if (xkb->ctrls->enabled_ctrls & XkbStickyKeysMask) { in _FixUpAction()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/netlogic/xlp/
H A Dnlm_hal.c2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
45 #include <asm/netlogic/xlp-hal/iomap.h>
46 #include <asm/netlogic/xlp-hal/xlp.h>
47 #include <asm/netlogic/xlp-hal/bridge.h>
48 #include <asm/netlogic/xlp-hal/pic.h>
49 #include <asm/netlogic/xlp-hal/sys.h>
58 nodep->coremask = 1; /* node 0, boot cpu */ in nlm_node_init()
59 nodep->sysbase = nlm_get_sys_regbase(node); in nlm_node_init()
60 nodep->picbase = nlm_get_pic_regbase(node); in nlm_node_init()
61 nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE; in nlm_node_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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