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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rv1126.c154 priv->pmucru, GPLL); in rv1126_gpll_get_pmuclk()
181 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_get_pmuclk() local
185 fracdiv = readl(&pmucru->pmu_clksel_con[13]); in rv1126_rtc32k_get_pmuclk()
197 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_set_pmuclk() local
200 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rv1126_rtc32k_set_pmuclk()
208 writel(val, &pmucru->pmu_clksel_con[13]); in rv1126_rtc32k_set_pmuclk()
216 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_i2c_get_pmuclk() local
221 con = readl(&pmucru->pmu_clksel_con[2]); in rv1126_i2c_get_pmuclk()
225 con = readl(&pmucru->pmu_clksel_con[3]); in rv1126_i2c_get_pmuclk()
238 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_i2c_set_pmuclk() local
[all …]
H A Dclk_rk3568.c128 printf("%s: could not find pmucru device\n", __func__); in rk3568_pmu_pll_set_rate()
134 pmu_priv->pmucru, pll_id, rate); in rk3568_pmu_pll_set_rate()
150 printf("%s: could not find pmucru device\n", __func__); in rk3568_pmu_pll_get_rate()
156 pmu_priv->pmucru, pll_id); in rk3568_pmu_pll_get_rate()
212 struct rk3568_pmucru *pmucru = priv->pmucru; in rk3568_rtc32k_get_pmuclk() local
216 fracdiv = readl(&pmucru->pmu_clksel_con[1]); in rk3568_rtc32k_get_pmuclk()
228 struct rk3568_pmucru *pmucru = priv->pmucru; in rk3568_rtc32k_set_pmuclk() local
231 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rk3568_rtc32k_set_pmuclk()
239 writel(val, &pmucru->pmu_clksel_con[1]); in rk3568_rtc32k_set_pmuclk()
247 struct rk3568_pmucru *pmucru = priv->pmucru; in rk3568_i2c_get_pmuclk() local
[all …]
H A Dclk_rk3399.c677 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
1599 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) in rk3399_i2c_get_pmuclk() argument
1605 con = readl(&pmucru->pmucru_clksel[2]); in rk3399_i2c_get_pmuclk()
1609 con = readl(&pmucru->pmucru_clksel[3]); in rk3399_i2c_get_pmuclk()
1613 con = readl(&pmucru->pmucru_clksel[2]); in rk3399_i2c_get_pmuclk()
1624 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, in rk3399_i2c_set_pmuclk() argument
1634 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), in rk3399_i2c_set_pmuclk()
1638 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), in rk3399_i2c_set_pmuclk()
1642 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), in rk3399_i2c_set_pmuclk()
1653 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) in rk3399_pwm_get_clk() argument
[all …]
H A Dclk_px30.c1220 printf("%s: could not find pmucru device\n", __func__); in px30_clk_get_gpll_rate()
1738 struct px30_pmucru *pmucru = priv->pmucru; in px30_pclk_pmu_get_pmuclk() local
1741 con = readl(&pmucru->pmu_clksel_con[0]); in px30_pclk_pmu_get_pmuclk()
1749 struct px30_pmucru *pmucru = priv->pmucru; in px30_pclk_pmu_set_pmuclk() local
1755 rk_clrsetreg(&pmucru->pmu_clksel_con[0], in px30_pclk_pmu_set_pmuclk()
1764 struct px30_pmucru *pmucru = priv->pmucru; in px30_gpll_get_pmuclk() local
1766 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); in px30_gpll_get_pmuclk()
1773 struct px30_pmucru *pmucru = priv->pmucru; in px30_gpll_set_pmuclk() local
1827 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); in px30_gpll_set_pmuclk()
1957 priv->pmucru = dev_read_addr_ptr(dev); in px30_pmuclk_ofdata_to_platdata()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1126.dtsi710 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
724 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
756 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
769 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
780 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
791 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
802 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
813 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
824 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
835 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
[all …]
H A Drk3568.dtsi533 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
546 pmucru: clock-controller@fdd00000 { label
547 compatible = "rockchip,rk3568-pmucru";
562 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>,
563 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
580 <&pmucru CLK_RTC32K_FRAC>;
586 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
600 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
616 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
627 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
[all …]
H A Drk3399.dtsi1092 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1105 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1118 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1120 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1133 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1135 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1151 clocks = <&pmucru PCLK_RKPWM_PMU>;
1162 clocks = <&pmucru PCLK_RKPWM_PMU>;
1173 clocks = <&pmucru PCLK_RKPWM_PMU>;
1184 clocks = <&pmucru PCLK_RKPWM_PMU>;
[all …]
H A D.rk3399-evb.dtb.dts.tmp
H A D.OK3568-C.dtb.dts.tmp
H A D.rk3399-firefly.dtb.dts.tmp
H A D.rk3399-puma-ddr1600.dtb.dts.tmp
H A D.rk3399-puma-ddr1866.dtb.dts.tmp
H A D.rk3399-puma-ddr1333.dtb.dts.tmp
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1126.dtsi903 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
917 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
950 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
963 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
974 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
985 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
996 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
1007 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
1018 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
1029 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
[all …]
H A Drv1126-evb-uvc.dtsi8 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
9 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
H A Drv1126-ai-cam.dtsi104 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
105 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.txt39 pmucru: clock-controller@ff2bc000 {
40 compatible = "rockchip,px30-pmucru";
61 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
H A Drockchip,rk3568-cru.txt9 - compatible: PMU for CRU should be "rockchip,rk3568-pmucru"
40 pmucru: clock-controller@fdd00000 {
41 compatible = "rockchip,rK3568-pmucru";
H A Drockchip,rv1126-cru.txt9 - compatible: PMU for CRU should be "rockchip,rv1126-pmucru"
42 pmucru: clock-controller@ff480000 {
43 compatible = "rockchip,rv1126-pmucru";
H A Drockchip,rk3399-cru.txt9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
43 pmucru: pmu-clock-controller@ff750000 {
44 compatible = "rockchip,rk3399-pmucru";
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3399-dmc.txt5 - rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3399/
H A Drk3399.c110 struct rk3399_pmucru *pmucru = (void *)PMUCRU_BASE; in arch_cpu_init() local
113 writel(0x7f002000, &pmucru->pmucru_clksel[1]); in arch_cpu_init()
114 writel(0x01000100, &pmucru->pmucru_clkgate_con[0]); in arch_cpu_init()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi828 clocks = <&pmucru XIN_OSC0_EDPPHY_G>;
854 pmucru: clock-controller@fdd00000 { label
855 compatible = "rockchip,rk3568-pmucru";
862 assigned-clocks = <&pmucru SCLK_32K_IOE>;
863 assigned-clock-parents = <&pmucru CLK_RTC_32K>;
874 <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
875 <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
876 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
914 <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
921 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
[all …]
H A Drk3399.dtsi1184 clocks = <&pmucru SCLK_PVTM_PMU>;
1186 resets = <&pmucru SRST_PVTM>;
1195 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1208 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1221 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1223 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1236 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1238 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1251 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1253 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
[all …]
H A Drk3399-vop-clk-set.dtsi42 assigned-clocks = <&pmucru SCLK_UART4_SRC>;
43 assigned-clock-parents = <&pmucru PLL_PPLL>;

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