Home
last modified time | relevance | path

Searched +full:pmu +full:- +full:sram (Results 1 – 25 of 138) sorted by relevance

123456

/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
35 static struct regmap *pmu; variable
43 ret = regmap_read(pmu, PMU_PWRDN_ST, &val); in pmu_power_domain_is_on()
57 np = dev->of_node; in rockchip_get_core_reset()
85 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); in pmu_set_power_domain()
92 ret = -1; in pmu_set_power_domain()
120 if (!sram_base_addr || (has_pmu && !pmu)) { in rockchip_boot_secondary()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sram/
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-meson/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
36 static struct regmap *pmu; variable
66 /* SMP SRAM */ in meson_smp_prepare_cpus()
69 pr_err("Missing SRAM node\n"); in meson_smp_prepare_cpus()
76 pr_err("Couldn't map SRAM registers\n"); in meson_smp_prepare_cpus()
80 /* PMU */ in meson_smp_prepare_cpus()
81 pmu = syscon_regmap_lookup_by_compatible(pmu_compatible); in meson_smp_prepare_cpus()
82 if (IS_ERR(pmu)) { in meson_smp_prepare_cpus()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
[all …]
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
H A Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
27 compatible = "arm,armv7-timer";
[all …]
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
[all …]
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/lantiq/
H A Ddanube.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "lantiq,biu", "simple-bus";
21 #interrupt-cells = <1>;
22 interrupt-controller;
33 sram@1f000000 {
34 #address-cells = <1>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3188.dtsi5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3188-cru.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
[all …]
H A Drk3288.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
18 interrupt-parent = <&gic>;
[all …]
H A D.rk3288-vyasa.dtb.dts.tmp
H A D.rk3288-rock2-square.dtb.dts.tmp
H A D.rk3288-evb.dtb.dts.tmp
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.txt1 Rockchip SRAM for IO Voltage Domains:
2 -------------------------------------
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
37 - "rockchip,rk3228-io-voltage-domain" for rk3228
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/k3.h>
12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Dhndsoc.h2 * Broadcom HND chip & on-chip-interconnect-related definitions.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/
H A Dhndsoc.h2 * Broadcom HND chip & on-chip-interconnect-related definitions.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Dhndsoc.h2 * Broadcom HND chip & on-chip-interconnect-related definitions.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Dhndsoc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Broadcom HND chip & on-chip-interconnect-related definitions.
5 * Copyright (C) 1999-2017, Broadcom Corporation
26 * <<Broadcom-WL-IPTag/Open:>>
28 * $Id: hndsoc.h 613129 2016-01-17 09:25:52Z $
62 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
67 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
77 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
78 #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */
79 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/
H A Dhndsoc.h2 * Broadcom HND chip & on-chip-interconnect-related definitions.
21 * <<Broadcom-WL-IPTag/Dual:>>
60 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
66 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
67 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
71 #define SI_GPV_SL4_BM_ADDR 0x44024 /* NIC-400 Slave interface 4 Bypass merge */
72 #define SI_GPV_SL6_BM_ADDR 0x46024 /* NIC-400 Slave interface 6 Bypass merge */
73 #define SI_GPV_SL8_BM_ADDR 0x4a024 /* NIC-400 Slave interface 8 Bypass merge */
74 #define SI_GPV_SL9_BM_ADDR 0x4b024 /* NIC-400 Slave interface 9 Bypass merge */
95 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Dhndsoc.h2 * Broadcom HND chip & on-chip-interconnect-related definitions.
21 * <<Broadcom-WL-IPTag/Dual:>>
60 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
66 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
67 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
71 #define SI_GPV_SL4_BM_ADDR 0x44024 /* NIC-400 Slave interface 4 Bypass merge */
72 #define SI_GPV_SL6_BM_ADDR 0x46024 /* NIC-400 Slave interface 6 Bypass merge */
73 #define SI_GPV_SL8_BM_ADDR 0x4a024 /* NIC-400 Slave interface 8 Bypass merge */
74 #define SI_GPV_SL9_BM_ADDR 0x4b024 /* NIC-400 Slave interface 9 Bypass merge */
95 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
[all …]

123456