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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun5i.dtsi157 pll6: clk@01c20028 { label
159 compatible = "allwinner,sun4i-a10-pll6-clk";
162 clock-output-names = "pll6_sata", "pll6_other", "pll6";
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
206 * Use PLL6 as parent, instead of CPU/AXI
210 assigned-clock-parents = <&pll6 1>;
225 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun6i-a31.dtsi68 clocks = <&pll6 0>;
76 clocks = <&pll6 0>;
203 pll6: clk@01c20028 { label
205 compatible = "allwinner,sun6i-a31-pll6-clk";
208 clock-output-names = "pll6", "pll6x2";
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
244 * controller requires AHB1 clocked from PLL6.
247 assigned-clock-parents = <&pll6 0>;
310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
[all …]
H A Dsun5i-gr8.dtsi157 pll6: clk@01c20028 { label
159 compatible = "allwinner,sun4i-a10-pll6-clk";
162 clock-output-names = "pll6_sata", "pll6_other", "pll6";
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
206 * Use PLL6 as parent, instead of CPU/AXI
210 assigned-clock-parents = <&pll6 1>;
225 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
293 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
309 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun4i-a10.dtsi257 pll6: clk@01c20028 { label
259 compatible = "allwinner,sun4i-a10-pll6-clk";
262 clock-output-names = "pll6_sata", "pll6_other", "pll6";
380 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
411 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun7i-a20.dtsi259 pll6: clk@01c20028 { label
261 compatible = "allwinner,sun4i-a10-pll6-clk";
264 clock-output-names = "pll6_sata", "pll6_other", "pll6",
297 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
316 * Use PLL6 as parent, instead of CPU/AXI
320 assigned-clock-parents = <&pll6 3>;
383 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun8i-a23-a33.dtsi63 clocks = <&pll6 0>;
131 pll6: clk@01c20028 { label
133 compatible = "allwinner,sun6i-a31-pll6-clk";
136 clock-output-names = "pll6", "pll6x2";
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
193 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
216 clocks = <&osc24M>, <&pll6 0>;
226 clocks = <&osc24M>, <&pll6 0>;
236 clocks = <&osc24M>, <&pll6 0>;
H A Dsun8i-a33.dtsi106 clocks = <&osc24M>, <&pll6 0>;
114 clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
H A Dsun8i-a23.dtsi82 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun6i-a31-pll6-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
23 const: allwinner,sun6i-a31-pll6-clk
47 compatible = "allwinner,sun6i-a31-pll6-clk";
50 clock-output-names = "pll6", "pll6x2";
H A Dallwinner,sun4i-a10-pll6-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
23 const: allwinner,sun4i-a10-pll6-clk
47 compatible = "allwinner,sun4i-a10-pll6-clk";
50 clock-output-names = "pll6_sata", "pll6_other", "pll6";
H A Dallwinner,sun4i-a10-mbus-clk.yaml50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
H A Dallwinner,sun4i-a10-usb-clk.yaml116 clocks = <&pll6 1>;
126 clocks = <&pll6 1>;
H A Dallwinner,sun5i-a13-ahb-clk.yaml48 clocks = <&axi>, <&cpu>, <&pll6 1>;
H A Dallwinner,sun4i-a10-apb1-clk.yaml48 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mod0-clk.yaml67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-ahb-clk.yaml95 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun6i.h25 u32 pll6_cfg; /* 0x28 pll6 control */
128 u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
142 u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
266 #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
268 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
368 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
432 #define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
434 #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
H A Dclock_sun8i_a83t.h27 u32 pll6_cfg; /* 0x28 pll6 peripheral control */
100 u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */
245 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
266 #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */
H A Dclock_sun4i.h25 u32 pll6_cfg; /* 0x28 pll6 control */
26 u32 pll6_tun; /* 0x2c pll6 tuning */
149 * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sunxi.c259 * can work at speeds up to 300M, just after reparenting to pll6 in sun5i_a13_get_ahb_factors()
284 * if parent is pll6, then
285 * parent_rate = pll6 rate / (m + 1)
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
919 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1121 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1128 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c54 * 3) The controller supports two different clocking strategies (PLL6 can
208 debug("Setting PLL6 to %d\n", DRAM_CLK * 2); in mctl_sys_init()
217 * PLL6 should be 2*CK * in mctl_sys_init()
221 * PLL6 should be CK/2 * in mctl_sys_init()
304 writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */ in mctl_sys_init()
311 * PLL6 should be 2*CK * in mctl_sys_init()
316 mctl_write_w(MC_RMCR, 0x2); * controller clock use pll6/4 * in mctl_sys_init()
322 mctl_write_w(MC_RMCR, 0x0); * controller clock use pll6 * in mctl_sys_init()
H A Ddram_sun4i.c306 /* PLL5P and PLL6 are the potential clock sources for MBUS */ in mctl_setup_dram_clock()
309 pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ in mctl_setup_dram_clock()
318 /* use PLL6 as the MBUS clock source */ in mctl_setup_dram_clock()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ata/
H A Dallwinner,sun4i-a10-ahci.yaml45 clocks = <&pll6 0>, <&ahb_gates 25>;
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-milbeaut.c23 #define M10V_PLL6 "pll6"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"

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