| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-usbdp.yaml | 55 dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
57 dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
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| H A D | ti,phy-am654-serdes.txt | 17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1046ardb/ |
| H A D | README | 18 - Lane1: XFI Cage
23 - Lane1: PCIe2 with PCIe x2 slot
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3588-vehicle-serdes-display-v21.dtsi | 645 0014 0008 //014h[3]-lane1 enable
860 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A
861 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B
1294 0014 0008 //014h[3]-lane1 enable
1708 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A
1709 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B
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| H A D | rk3568.dtsi | 2506 /* rockchip,bifurcation; lane1 when using 1+1 */
3558 physical lanes use lane0 and lane1,
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| /OK3568_Linux_fs/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 24 - Lane1: x1 PCIe standard slot
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 243 uint8_t lane1:2; /* Mapping for lane 1 */ member
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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| /OK3568_Linux_fs/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dphy-rx0.c | 213 /* HS RX Control of lane1 */ in rk_dphy_enable()
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| H A D | phy-rockchip-inno-combphy.c | 269 /* Set rxtermination for lane1 */ in phy_pcie_init()
325 /* Disable PHY lane1 which isn't needed for USB3 */ in phy_u3_init()
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| H A D | phy-rockchip-typec.c | 698 * Lane1 (tx_rx_p/m_ln_1) RX1+/RX1- (pins B11/B10)
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| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | zynqmp.dtsi | 740 lane1: lane1 { label
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| H A D | rk3568.dtsi | 1722 /* rockchip,bifurcation; lane1 when using 1+1 */
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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| /OK3568_Linux_fs/kernel/drivers/scsi/ufs/ |
| H A D | ufs-hisi.c | 60 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
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| H A D | ufs-qcom.c | 179 /* In case of single lane per direction, don't read lane1 clocks */ in ufs_qcom_init_lane_clks()
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/ |
| H A D | msm8996.dtsi | 389 reset-names = "lane1";
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_link_dp.c | 1422 lt_result = "CR failed lane1"; in print_status_message()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 4113 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
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| /OK3568_Linux_fs/external/libmali/lib/arm-linux-gnueabihf/ |
| HD | libmali-midgard-t76x-r18p0-r1p0-gbm.so | d t u x y v w p r q s ` a GL_ARM_rgba8 GL_ARM_mali_shader_binary GL_OES_depth24 GL_OES_depth_texture GL_OES_depth_texture_cube_map GL_OES_packed_depth_stencil GL_OES_rgb8_rgba8 ... |
| HD | libmali-midgard-t76x-r18p0-r0p0-wayland-gbm.so | compiler_type openglessl shader_type compute fragment vertex tessellation_control tessellation_evaluation geometry define undefine variants deserialized_outfile print_cycle_counts #define %s # ... |
| HD | libmali-midgard-t76x-r18p0-r0p0-gbm.so | 01234567 cutils_cstr_strncat cutils_cstr_strncpy 0X 0123456789abcdef 0123456789ABCDEF In file: cutils/cstr/src/mali_cutils_cstr ... |
| HD | libmali-midgard-t76x-r18p0-r0p0-x11-gbm.so | @ADEPQTU CBGFSRWV LMHI\]XY ONKJ_^[Z0145 !$%pqtu`ade3276#"'&srwvcbgf< ... |