| /OK3568_Linux_fs/kernel/drivers/phy/amlogic/ |
| H A D | phy-meson-g12a-usb3-pcie.c | 215 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus in phy_g12a_usb3_init()
228 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in phy_g12a_usb3_init()
229 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in phy_g12a_usb3_init()
230 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 in phy_g12a_usb3_init()
231 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in phy_g12a_usb3_init()
248 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 in phy_g12a_usb3_init()
249 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 in phy_g12a_usb3_init()
250 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in phy_g12a_usb3_init()
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| /OK3568_Linux_fs/kernel/drivers/phy/qualcomm/ |
| H A D | phy-qcom-ipq806x-usb.c | 345 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode in qcom_ipq806x_usb_ss_phy_init()
368 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in qcom_ipq806x_usb_ss_phy_init()
369 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
370 * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
371 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
389 * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
390 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 in qcom_ipq806x_usb_ss_phy_init()
391 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in qcom_ipq806x_usb_ss_phy_init()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/ |
| H A D | ti,phy-am654-serdes.txt | 13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
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| H A D | phy-rockchip-usbdp.yaml | 54 have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
56 "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1046ardb/ |
| H A D | README | 17 - Lane0: XFI with x1 RJ45 connector
22 - Lane0: PCIe1 with miniPCIe slot
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | rv1106-evb-dual-cam.dtsi | 6 * v1.0.0 os04a10 0x36 lane0~1(dphy1)
8 * v1.1.0 gc2053 0x37 lane0~1(dphy1)
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| H A D | rv1106-evb-cvr-dual-cam.dtsi | 6 * v1.0.0 sc530ai 0x30 lane0~1(dphy1)
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
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| /OK3568_Linux_fs/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-combphy.c | 267 /* Set rxtermination for lane0 */ in phy_pcie_init()
321 * sel operation, otherwise, the PIPE PHY status lane0 in phy_u3_init()
370 /* Wait PIPE PHY status lane0 ready */ in phy_u3_init()
375 dev_err(priv->dev, "wait phy status lane0 ready timeout\n"); in phy_u3_init()
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| H A D | phy-rockchip-dphy-rx0.c | 211 /* HS RX Control of lane0 */ in rk_dphy_enable()
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| H A D | phy-rockchip-mipi-rx.c | 1226 * step10.2:set hsfreqrange by lane0(test code 0x44) in mipidphy_rx_stream_on()
1340 * step10.2:set hsfreqrange by lane0(test code 0x44) in mipidphy_txrx_stream_on()
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3566-evb2-lp4x-v10.dtsi | 259 /* split mode: lane0/1 */
309 /* full mode: lane0-3 */
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| H A D | rk3566-evb-mipitest-v10.dtsi | 239 /* split mode: lane0/1 */
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| H A D | rk3566-evb1-ddr4-v10.dtsi | 234 /* split mode: lane0/1 */
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/ |
| H A D | k3-j721e-main.dtsi | 81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
86 /* SERDES4 lane0/1/2/3 select */
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| H A D | k3-j7200-main.dtsi | 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
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| /OK3568_Linux_fs/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 23 - Lane0: x1 mini-PCIe slot
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| /OK3568_Linux_fs/u-boot/board/theadorable/ |
| H A D | theadorable.c | 103 * Lane0 - PCIE0.0 X1 (to WIFI Module)
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 242 uint8_t lane0:2; /* Mapping for lane 0 */ member
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | zynqmp.dtsi | 737 lane0: lane0 { label
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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| /OK3568_Linux_fs/kernel/drivers/scsi/ufs/ |
| H A D | ufs-hisi.c | 60 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
| H A D | high_speed_env_lib.c | 390 reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */ in serdes_phy_config()
391 …DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) … in serdes_phy_config()
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| /OK3568_Linux_fs/kernel/drivers/phy/samsung/ |
| H A D | phy-exynos5-usbdrd.c | 656 * register LANE0.TX_DEBUG which is internal to PHY. in exynos5420_usbdrd_phy_calibrate()
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