Home
last modified time | relevance | path

Searched +full:init +full:- +full:delay (Results 1 – 25 of 1126) sorted by relevance

12345678910>>...46

/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
82 u32 delay; in rockchip_mmc_set_phase() local
98 return -EINVAL; in rockchip_mmc_set_phase()
105 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
113 * On one extreme (if delay is actually 44ps): in rockchip_mmc_set_phase()
115 * The other (if delay is actually 77ps): in rockchip_mmc_set_phase()
[all …]
H A Dclk-pvtm.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/delay.h>
17 #include <linux/clk-provider.h>
60 static void rockchip_clock_pvtm_delay(unsigned int delay) in rockchip_clock_pvtm_delay() argument
62 unsigned int ms = delay / 1000; in rockchip_clock_pvtm_delay()
63 unsigned int us = delay % 1000; in rockchip_clock_pvtm_delay()
82 ret = regmap_write(pvtm->grf, pvtm->info->sel_con, in rockchip_clock_sel_internal_pvtm()
83 wr_msk_bit(pvtm->info->sel_value, in rockchip_clock_sel_internal_pvtm()
84 pvtm->info->sel_shift, in rockchip_clock_sel_internal_pvtm()
85 pvtm->info->sel_mask)); in rockchip_clock_sel_internal_pvtm()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-apbc.c15 #include <linux/delay.h>
30 unsigned int delay; member
45 if (apbc->lock) in clk_apbc_prepare()
46 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
48 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
49 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
52 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
54 if (apbc->lock) in clk_apbc_prepare()
55 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
57 udelay(apbc->delay); in clk_apbc_prepare()
[all …]
H A Dclk-gate.c12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
43 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_rgb.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/media-bus-format.h>
79 u8 delay; member
108 unsigned int init; member
109 } delay; member
138 struct rockchip_rgb *rgb = dev_get_priv(conn->dev); in rockchip_rgb_connector_prepare()
139 struct crtc_state *crtc_state = &state->crtc_state; in rockchip_rgb_connector_prepare()
140 int pipe = crtc_state->crtc_id; in rockchip_rgb_connector_prepare()
143 pinctrl_select_state(rgb->dev, "default"); in rockchip_rgb_connector_prepare()
[all …]
H A Drockchip_panel.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
20 #include <dm/uclass-id.h>
21 #include <linux/media-bus-format.h>
56 unsigned int init; member
57 } delay; member
81 return -EINVAL; in get_panel_cmd_type()
105 buf += sizeof(*header) + header->payload_length; in rockchip_panel_parse_cmds()
106 len -= sizeof(*header) + header->payload_length; in rockchip_panel_parse_cmds()
110 pcmds->cmds = calloc(cnt, sizeof(struct rockchip_cmd_desc)); in rockchip_panel_parse_cmds()
[all …]
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/strace/strace/
H A Dskip-load.patch4 Upstream-Status: Inappropriate
5 Signed-off-by: Ross Burton <ross.burton@arm.com>
7 diff --git a/tests/clock_nanosleep.gen.test b/tests/clock_nanosleep.gen.test
9 --- a/tests/clock_nanosleep.gen.test
11 @@ -1,4 +1,5 @@
12 #!/bin/sh -efu
13 …# Generated by ./tests/gen_tests.sh from ./tests/gen_tests.in (clock_nanosleep -e trace=clock_nano…
14 . "${srcdir=.}/init.sh"
16 run_strace_match_diff -e trace=clock_nanosleep,clock_gettime
17 diff --git a/tests/delay.test b/tests/delay.test
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmiiphybb.c3 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 * This provides a bit-banged interface to the ethernet MII management
95 .init = bb_mii_init_wrap,
101 .delay = bb_delay_wrap,
116 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); in bb_miiphy_init()
117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); in bb_miiphy_init()
118 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); in bb_miiphy_init()
119 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); in bb_miiphy_init()
120 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); in bb_miiphy_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_rgb.c1 // SPDX-License-Identifier: GPL-2.0
5 * Sandy Huang <hjc@rock-chips.com>
77 u8 delay; member
107 unsigned int init; member
108 } delay; member
174 struct rockchip_drm_private *private = connector->dev->dev_private; in rockchip_rgb_atomic_connector_get_property()
176 if (property == private->connector_id_prop) { in rockchip_rgb_atomic_connector_get_property()
177 *val = rgb->id; in rockchip_rgb_atomic_connector_get_property()
182 return -EINVAL; in rockchip_rgb_atomic_connector_get_property()
198 struct drm_panel *panel = rgb->panel; in rockchip_rgb_connector_get_modes()
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dehci-tegra.c3 * Copyright (c) 2009-2015 NVIDIA Corporation
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm-generic/gpio.h>
15 #include <asm/arch-tegra/usb.h>
16 #include <asm/arch-tegra/clk_rst.h>
44 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
45 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
46 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
47 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
48 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/panel/
H A Dsamsung,s6e8aa0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h4 * SPDX-License-Identifier: GPL-2.0
11 * STATIC_TRAINING - Set only if static parameters for training are set and
61 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
63 /*init DRAM */
134 {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */
136 /*init DRAM */
188 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
190 /*init DRAM */
241 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
243 /*init DRAM */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
101 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
105 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
/OK3568_Linux_fs/yocto/poky/meta/lib/oeqa/sdk/buildtools-cases/
H A Dbuild.py2 # SPDX-License-Identifier: MIT
16 with tempfile.TemporaryDirectory(prefix='bitbake-build-', dir=self.tc.sdk_dir) as testdir:
19 self._run('. %s/oe-init-build-env %s' % (corebase, testdir))
25 self._run('. %s/oe-init-build-env %s && bitbake virtual/libc' % (corebase, testdir))
27 delay = 10
28 …while delay and (os.path.exists(testdir + "/bitbake.lock") or os.path.exists(testdir + "/cache/has…
30 delay = delay - 1
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_static.c4 * SPDX-License-Identifier: GPL-2.0
16 u32 g_zpri_data = 123; /* controller data - P drive strength */
17 u32 g_znri_data = 123; /* controller data - N drive strength */
18 u32 g_zpri_ctrl = 74; /* controller C/A - P drive strength */
19 u32 g_znri_ctrl = 74; /* controller C/A - N drive strength */
20 u32 g_zpodt_data = 45; /* controller data - P ODT */
21 u32 g_znodt_data = 45; /* controller data - N ODT */
22 u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
23 u32 g_znodt_ctrl = 45; /* controller data - N ODT */
37 /* debug delay in write leveling */
[all …]
/OK3568_Linux_fs/u-boot/cmd/
H A Dbootmenu.c2 * (C) Copyright 2011-2013 Pali Rohár <pali.rohar@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
35 int delay; /* delay for autoboot */ member
62 int reverse = (entry->menu->active == entry->num); in bootmenu_print_entry()
65 * Move cursor to line where the entry will be drown (entry->num) in bootmenu_print_entry()
68 printf(ANSI_CURSOR_POSITION, entry->num + 4, 1); in bootmenu_print_entry()
75 puts(entry->title); in bootmenu_print_entry()
86 if (menu->delay > 0) { in bootmenu_autoboot_loop()
87 printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); in bootmenu_autoboot_loop()
88 printf(" Hit any key to stop autoboot: %2d ", menu->delay); in bootmenu_autoboot_loop()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-palmas.c5 * Copyright (c) 2013-2014 Texas Instruments, Inc.
21 #include <linux/clk-provider.h>
39 int delay; member
66 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
67 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
68 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
69 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
71 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
72 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
73 else if (cinfo->clk_desc->delay) in palmas_clks_prepare()
[all …]
/OK3568_Linux_fs/u-boot/drivers/misc/
H A Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/delay.h>
15 #include <rockchip-otp.h>
18 int (*init)(struct udevice *dev); member
25 int delay = OTPC_TIMEOUT; in rockchip_otp_wait_status() local
27 while (!(readl(otp->base + OTPC_INT_STATUS) & flag)) { in rockchip_otp_wait_status()
29 delay--; in rockchip_otp_wait_status()
30 if (delay <= 0) { in rockchip_otp_wait_status()
31 printf("%s: wait init status timeout\n", __func__); in rockchip_otp_wait_status()
32 return -ETIMEDOUT; in rockchip_otp_wait_status()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dbt819.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
21 #include <linux/delay.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Dpx30-evb-ddr3-v10-linux.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rk3326-linux.dtsi"
9 #include "px30-evb-ddr3-v10.dtsi"
13 compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30";
15 /delete-node/ test-power;
22 compatible = "sitronix,st7703", "simple-panel-dsi";
24 power-supply = <&vcc3v3_lcd>;
26 prepare-delay-ms = <2>;
27 reset-delay-ms = <1>;
[all …]
H A Dpx30-evb-ddr3-v10.dts4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "px30-android.dtsi"
10 #include "px30-evb-ddr3-v10.dtsi"
14 compatible = "rockchip,px30-evb-ddr3-v10", "rockchip,px30";
21 compatible = "sitronix,st7703", "simple-panel-dsi";
23 power-supply = <&vcc3v3_lcd>;
25 prepare-delay-ms = <2>;
26 reset-delay-ms = <1>;
27 init-delay-ms = <20>;
[all …]
H A Dpx30-z7-a0-rk618-dsi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/display/drm_mipi_dsi.h>
11 #include <dt-bindings/display/media-bus-format.h>
12 #include <dt-bindings/clock/rk618-cru.h>
14 #include "px30-android.dtsi"
18 compatible = "rockchip,px30-z7-a0", "rockchip,px30";
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/extcon-provider.h>
165 return -EINVAL; in otg_mode_show()
168 switch (rk_phy->mode) { in otg_mode_show()
181 return -EINVAL; in otg_mode_show()
194 return -EINVAL; in otg_mode_store()
197 mutex_lock(&rk_phy->mutex); in otg_mode_store()
[all …]

12345678910>>...46