Searched +full:imx7d +full:- +full:src (Results 1 – 19 of 19) sorted by relevance
5 * This file is dual-licensed: you can use it either under the terms44 #include <dt-bindings/clock/imx7d-clock.h>45 #include <dt-bindings/gpio/gpio.h>46 #include <dt-bindings/input/input.h>47 #include <dt-bindings/interrupt-controller/arm-gic.h>48 #include "imx7d-pinfunc.h"51 #address-cells = <1>;52 #size-cells = <1>;55 * pre-existing /chosen node to be available to insert the57 * Also for U-Boot there must be a pre-existing /memory node.[all …]
9 #include <dt-bindings/clock/imx6sll-clock.h>10 #include <dt-bindings/gpio/gpio.h>11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include "imx6sll-pinfunc.h"43 #address-cells = <1>;44 #size-cells = <0>;47 compatible = "arm,cortex-a9";50 next-level-cache = <&L2>;51 operating-points = <58 fsl,soc-operating-points = <[all …]
2 * Copyright 2015-2016 Freescale Semiconductor, Inc.9 #include <dt-bindings/clock/imx6ul-clock.h>10 #include <dt-bindings/gpio/gpio.h>11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include "imx6ull-pinfunc.h"13 #include "imx6ull-pinfunc-snvs.h"50 #address-cells = <1>;51 #size-cells = <0>;54 compatible = "arm,cortex-a7";57 clock-latency = <61036>; /* two CLK32 periods */[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT7 #include <dt-bindings/reset/imx7-reset.h>12 clock-frequency = <996000000>;13 operating-points-v2 = <&cpu0_opp_table>;14 #cooling-cells = <2>;15 nvmem-cells = <&fuse_grade>;16 nvmem-cell-names = "speed_grade";20 compatible = "arm,cortex-a7";23 clock-frequency = <996000000>;24 operating-points-v2 = <&cpu0_opp_table>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT6 #include <dt-bindings/clock/imx7d-clock.h>7 #include <dt-bindings/power/imx7-power.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/input/input.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/reset/imx7-reset.h>12 #include "imx7d-pinfunc.h"15 #address-cells = <1>;16 #size-cells = <1>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Andrey Smirnov <andrew.smirnov@gmail.com>19 <dt-bindings/reset/imx7-reset.h> for i.MX7,20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.26 - items:27 - enum:[all …]
1 NXP iMX6SX/iMX7D Co-Processor Bindings2 ----------------------------------------4 This binding provides support for ARM Cortex M4 Co-processor found on some8 - compatible Should be one of:9 "fsl,imx7d-cm4"10 "fsl,imx6sx-cm4"11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)12 - syscon Phandle to syscon block which provide access to16 - memory-region list of phandels to the reserved memory regions.17 (See: ../reserved-memory/reserved-memory.txt)[all …]
4 and thus inherits all the common properties defined in designware-pcie.txt.7 - compatible:8 - "fsl,imx6q-pcie"9 - "fsl,imx6sx-pcie",10 - "fsl,imx6qp-pcie"11 - "fsl,imx7d-pcie"12 - "fsl,imx8mq-pcie"13 - reg: base address and length of the PCIe controller14 - interrupts: A list of interrupt outputs of the controller. Must contain an15 entry for each entry in the interrupt-names property.[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/imx8mn-clock.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/input/input.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>12 #include "imx8mn-pinfunc.h"15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/imx8mm-clock.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/input/input.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>12 #include "imx8mm-pinfunc.h"15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>7 #include <dt-bindings/clock/imx8mq-clock.h>8 #include <dt-bindings/power/imx8mq-power.h>9 #include <dt-bindings/reset/imx8mq-reset.h>10 #include <dt-bindings/gpio/gpio.h>11 #include "dt-bindings/input/input.h"12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/thermal/thermal.h>14 #include "imx8mq-pinfunc.h"[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/imx8mp-clock.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/input/input.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>12 #include "imx8mp-pinfunc.h"15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-y := cpu.o system.o irq-common.o4 obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o6 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o8 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o9 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o11 imx5-pm-$(CONFIG_PM) += pm-imx5.o12 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)14 obj-$(CONFIG_MXC_TZIC) += tzic.o15 obj-$(CONFIG_MXC_AVIC) += avic.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.4 * Copyright 2017-2018 NXP.103 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); in imx_init_revision_from_anatop()106 if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) in imx_init_revision_from_anatop()108 if (of_device_is_compatible(np, "fsl,imx7d-anatop")) in imx_init_revision_from_anatop()117 if (of_device_is_compatible(np, "fsl,imx7d-anatop")) { in imx_init_revision_from_anatop()138 "fsl,imx6ul-src"); in imx_init_revision_from_anatop()160 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); in imx_anatop_init()162 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); in imx_anatop_init()
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/thermal/imx-thermal.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Shawn Guo <shawnguo@kernel.org>11 - Anson Huang <Anson.Huang@nxp.com>16 - fsl,imx6q-tempmon17 - fsl,imx6sx-tempmon18 - fsl,imx7d-tempmon28 be configured to auto reboot by SRC module for IRQ_PANIC. IRQ_HIGH,[all …]
1 // SPDX-License-Identifier: GPL-2.0-only5 * i.MX7 System Reset Controller (SRC) driver14 #include <linux/reset-controller.h>16 #include <dt-bindings/reset/imx7-reset.h>17 #include <dt-bindings/reset/imx8mq-reset.h>18 #include <dt-bindings/reset/imx8mp-reset.h>51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update()53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update()54 signal->offset, signal->bit, value); in imx7_reset_update()95 const unsigned int bit = imx7src->signals[id].bit; in imx7_reset_set()[all …]
4 * SPDX-License-Identifier: GPL-2.0+9 #include <asm/arch/imx-regs.h>12 #include <asm/mach-imx/boot_mode.h>13 #include <asm/mach-imx/dma.h>14 #include <asm/mach-imx/hab.h>15 #include <asm/mach-imx/rdc-sema.h>16 #include <asm/arch/imx-rdc.h>39 * at A7 core side. At default, all resources are in domain 0 - 3.102 * defines a 2-bit SPEED_GRADING113 struct fuse_bank *bank = &ocotp->bank[1]; in get_cpu_speed_grade_hz()[all …]
2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net9 * SPDX-License-Identifier: GPL-2.0+25 #include <asm-generic/gpio.h>99 * @non_removable: 0: removable; 1: non-removable132 if (data->blocks > 1) { in esdhc_xfertyp()140 if (data->flags & MMC_DATA_READ) in esdhc_xfertyp()144 if (cmd->resp_type & MMC_RSP_CRC) in esdhc_xfertyp()146 if (cmd->resp_type & MMC_RSP_OPCODE) in esdhc_xfertyp()148 if (cmd->resp_type & MMC_RSP_136) in esdhc_xfertyp()[all …]
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