Searched +full:imx5 +full:- +full:clock (Results 1 – 14 of 14) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/imx5-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Clock bindings for Freescale i.MX510 - Fabio Estevam <fabio.estevam@nxp.com>13 The clock consumer should specify the desired clock by having the clock14 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h15 for the full list of i.MX5 clock IDs.20 - fsl,imx53-ccm[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/rtc/rtc-mxc_v2.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: i.MX53 Secure Real Time Clock (SRTC)10 - $ref: "rtc.yaml#"13 - Patrick Bruenn <p.bruenn@beckhoff.com>18 - fsl,imx53-rtc30 - compatible31 - reg[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Philipp Zabel <p.zabel@pengutronix.de>13 "#pwm-cells":18 - 219 - 323 - enum:24 - fsl,imx1-pwm[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/w1/fsl-imx-owire.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Martin Fuzzey <mfuzzey@parkeon.com>15 - const: fsl,imx21-owire16 - items:17 - enum:18 - fsl,imx27-owire19 - fsl,imx50-owire[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/nvmem/imx-iim.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Anson Huang <Anson.Huang@nxp.com>17 - $ref: "nvmem.yaml#"22 - fsl,imx25-iim23 - fsl,imx27-iim24 - fsl,imx31-iim25 - fsl,imx35-iim[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX10 - Wolfram Sang <wolfram@the-dreams.de>13 - $ref: /schemas/i2c/i2c-controller.yaml#18 - const: fsl,imx1-i2c19 - const: fsl,imx21-i2c20 - const: fsl,vf610-i2c[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Shawn Guo <shawnguo@kernel.org>13 - $ref: "/schemas/spi/spi-controller.yaml#"18 - const: fsl,imx1-cspi19 - const: fsl,imx21-cspi20 - const: fsl,imx27-cspi21 - const: fsl,imx31-cspi[all …]
10 * http://www.opensource.org/licenses/gpl-license.html15 #include "imx53-pinfunc.h"16 #include <dt-bindings/clock/imx5-clock.h>17 #include <dt-bindings/gpio/gpio.h>18 #include <dt-bindings/input/input.h>19 #include <dt-bindings/interrupt-controller/irq.h>27 #address-cells = <1>;28 #size-cells = <1>;29 compatible = "simple-bus";33 compatible = "fsl,aips-bus", "simple-bus";[all …]
1 Device-Tree bindings for LVDS Display Bridge (ldb)6 The LVDS Display Bridge device tree node contains up to two lvds-channel10 - #address-cells : should be <1>11 - #size-cells : should be <0>12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.17 The phandle points to the iomuxc-gpr region containing the LVDS19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to21 Documentation/devicetree/bindings/clock/clock-bindings.txt23 "di0_pll" - LDB LVDS channel 0 mux[all …]
1 // SPDX-License-Identifier: GPL-2.0+7 #include "imx50-pinfunc.h"8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/clock/imx5-clock.h>12 #address-cells = <1>;13 #size-cells = <1>;16 * pre-existing /chosen node to be available to insert the47 #address-cells = <1>;48 #size-cells = <0>;51 compatible = "arm,cortex-a8";[all …]
1 // SPDX-License-Identifier: GPL-2.0+6 #include "imx51-pinfunc.h"7 #include <dt-bindings/clock/imx5-clock.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/input/input.h>10 #include <dt-bindings/interrupt-controller/irq.h>13 #address-cells = <1>;14 #size-cells = <1>;17 * pre-existing /chosen node to be available to insert the42 tzic: tz-interrupt-controller@e0000000 {[all …]
1 // SPDX-License-Identifier: GPL-2.0+6 #include "imx53-pinfunc.h"7 #include <dt-bindings/clock/imx5-clock.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/input/input.h>10 #include <dt-bindings/interrupt-controller/irq.h>13 #address-cells = <1>;14 #size-cells = <1>;17 * pre-existing /chosen node to be available to insert the50 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only10 #include <linux/clk-provider.h>17 #include <dt-bindings/clock/imx5-clock.h>65 /* Low-power Audio Playback Mode clock */304 * This clock is called periph_clk in the i.MX50 Reference Manual, but in mx50_clocks_init()350 /* set SDHC root clock to 200MHZ*/ in mx50_clocks_init()363 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);444 /* set SDHC root clock to 166.25MHZ*/ in mx51_clocks_init()457 * enabled without the IPU clock being enabled aswell. in mx51_clocks_init()469 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);[all …]
... arm926ejs/mxs/clock.c u-boot-2021.07/arch/arm/cpu/arm926ejs/ ...